Compliant printed circuit wafer level semiconductor package

A wafer-level semiconductor package comprising:

• a wafer including a plurality of semiconductor devices;
• at least one dielectric layer selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices;
• a conductive material printed in the first recesses forming contact members on the semiconductor devices;
• at least one dielectric layer selectively printed to create a plurality of second recesses corresponding to a target circuit geometry;
• and
• a conductive material printed in at least a portion of the second recesses comprising circuit geometry, the circuit geometry comprising a plurality of exposed terminals adapted to electrically couple to another circuit member;
• and
• a plurality of discrete packaged semiconductor devices cut from the wafer.

A method of making a wafer-level semiconductor package, the method comprising the step of:

• printing at least one dielectric layer selectively on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices;
• printing a conductive material in a plurality of the first recesses to form contact members on the semiconductor devices;
• printing at least one dielectric layer selectively on at least a portion of the wafer to create a plurality of second recesses corresponding to a target circuit geometry;
• printing a conductive material in at least a portion of the second recesses to form a circuit geometry, the circuit geometry comprising a plurality of exposed terminals electrically coupled to the semiconductor devices;
• and
• dicing the wafer into a plurality of discrete packaged semiconductor devices.