Embedded package and method for manufacturing the same

A method for manufacturing an embedded package, comprising:

• preparing first and second semiconductor chips wherein each of the first and second semiconductor chips has a sunken area at a side surface;
• forming a first cavity by etching a third surface of a first sub core layer, wherein the first sub core layer has a first surface and a third surface, wherein a first circuit pattern is formed over the third surface, and a second circuit pattern is formed over the first surface;
• mounting the first semiconductor chip in the first cavity such that a first bump of the first semiconductor chip is exposed on the third surface of the first sub core layer and electrically connected with the first circuit patterns;
• forming a second cavity by etching a fourth surface of a second sub core layer, wherein the second sub core layer has a second surface and a fourth surface, wherein a third circuit pattern is formed over the second surface;
• mounting the second semiconductor chip in the second cavity such that a second bump of the second semiconductor chip is exposed on the fourth surface of the second sub core layer and electrically connected with the first circuit patterns;
• attaching the second sub core layer mounted with the second semiconductor chip onto the first sub core layer mounted with the first semiconductor chip such that the first bump of the first semiconductor chip and the second bump of the second semiconductor chip are connected with each other;
• and
• forming a first via through the second circuit pattern and the first sub core layer such that the first via electrically connects the second circuit pattern and the first circuit pattern with each other, and a second via through the third circuit pattern and the second sub core layer such that the second via electrically connects the third circuit pattern and the first circuit pattern with each other.