High performance low power bulk fet device and method of manufacture
AssigneeInternational Business Machines Corporation
InventorsJin CAI, Toshiharu FURUKAWA, Robert R. ROBISON
Life of this patent
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Abstract
A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.
Claims20
A method of forming a semiconductor device, comprising:
- forming a channel of a field effect transistor (FET) in a substrate;
- forming a heavily doped region in the substrate;
- forming recesses adjacent the channel and the heavily doped region;
- forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region;
- and
- forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.
A method of forming a semiconductor device, comprising:
- forming a first layer on a substrate, wherein the first layer has a first dopant concentration;
- forming a second layer on the first layer, wherein the second layer has a second dopant concentration less than the doping concentration of the first layer;
- forming a gate of a field effect transistor (FET) on the second layer;
- forming a mask on portions of the second layer adjacent the gate;
- removing regions of the first layer and the second layer adjacent the masked portions, wherein the removing exposes surfaces of the substrate, first layer and second layer;
- forming a third layer on the exposed surfaces of the substrate, first layer and second layer, wherein a third dopant concentration of the third layer is less than the first dopant concentration;
- and
- forming a source and drain regions on the third layer.
A semiconductor structure, comprising:
- a field effect transistor (FET) including a channel in a substrate;
- a heavily doped region in the substrate;
- an undoped or lightly doped intermediate layer on the heavily doped region;
- and
- source and drain regions of the FET on the intermediate layer,
- wherein the intermediate layer is between the channel and the source and drain regions;
- and
- the intermediate layer is between the heavily doped region and the source and drain regions.
Dependencies are inferred from the claim text.