Novel device scheme of hmkg gate-last process

An integrated circuit having metal gate stacks, comprising:

• a semiconductor substrate;
• a first gate stack of an n-type field-effect transistor, the first gate stack including:
• a high k dielectric layer on the semiconductor substrate;
• a titanium nitride layer on the high k dielectric material layer;
• a first metal layer on the titanium nitride layer;
• and
• a second metal layer on the first metal layer;
• and
• a second gate stack of a p-type FET, the second gate stack including:
• the high k dielectric layer on the semiconductor substrate;
• the titanium nitride layer on the high k dielectric material layer;
• a third metal layer on the titanium nitride layer, wherein the third metal layer is different from the first and second metal layers;
• and
• a fourth metal layer on the third metal layer.

An integrated circuit comprising:

• a semiconductor substrate;
• a first gate stack of an n-type field-effect transistor, the first gate stack including:
• a high k dielectric layer on the semiconductor substrate;
• a first metal layer disposed over the high k dielectric material layer;
• a second metal layer on the first metal layer, the second metal layer being different than the first metal layer;
• and
• a third metal layer on the second metal layer, the third metal layer being different than the second metal layer;
• and
• a second gate stack of a p-type FET, the second gate stack including:
• the high k dielectric layer on the semiconductor substrate;
• the first metal layer disposed over the high k dielectric material layer;
• a fourth metal layer on the first metal layer, the fourth metal layer being different than the first metal layer;
• and
• a fifth metal layer on the fourth metal layer, the fifth metal layer being different than the fourth metal layer.

An integrated circuit comprising:

• a semiconductor substrate;
• a first gate stack of an n-type field-effect transistor, the first gate stack including:
• a high k dielectric layer on the semiconductor substrate;
• a titanium nitride layer disposed on the high k dielectric material layer;
• a first metal layer on the titanium nitride layer, the first metal layer being different than the titanium nitride layer;
• and
• a second metal layer on the first metal layer, the second metal layer being different than the first metal layer;
• and
• a second gate stack of a p-type FET, the second gate stack including:
• the high k dielectric layer on the semiconductor substrate;
• the titanium nitride layer on the high k dielectric material layer;
• a third metal layer disposed over the titanium nitride layer;
• and
• a fourth metal layer on the third metal layer, the fourth metal layer being different than the third metal layer.