US 2012/0056268 A1Published application

Semiconductor device and manufacturing method thereof

AssigneeRenesas Electronics Corporation

InventorsMasaharu MIZUTANI, Masaru KADOSHIMA, Takaaki KAWAHARA, Masao INOUE, Hiroshi UMEDA

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Abstract

There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.

Claims28

Dependent claims

A semiconductor device, comprising:

an n-channel MISFET formed in an n-channel MISFET formation region of a semiconductor substrate;
and
a p-channel MISFET formed in a p-channel MISFET formation region of the semiconductor substrate,
wherein the n-channel MISFET has:
(a) a first insulating film formed over the semiconductor substrate, and containing hafnium and zirconium;
(b) a first gate electrode formed over the first insulating film;
(c) a first source region formed in the semiconductor substrate;
and
(d) a first drain region formed in the semiconductor substrate,
wherein the p-channel MISFET has:
(e) a second insulating film formed over the semiconductor substrate, and containing hafnium;
(f) a second gate electrode formed over the second insulating film;
(g) a second source region formed in the semiconductor substrate;
and
(h) a second drain region formed in the semiconductor substrate,
wherein a physical film thickness of the first insulating film is larger than a physical film thickness of the second insulating film, and
wherein a concentration of the zirconium contained in the first insulating film is higher than a concentration of the zirconium contained in the second insulating film.

14 more elements

A method of manufacturing a semiconductor device comprising an n-channel MISFET formed in an n-channel MISFET formation region of a semiconductor substrate, and a p-channel MISFET formed in a p-channel MISFET formation region of the semiconductor substrate, the method comprising the steps of:

(a) forming a second insulating film containing hafnium over the semiconductor substrate;
(b) after the step (a), forming a hard mask film over the second insulating film;
(c) after the step (b), patterning the hard mask film to remove the hard mask film formed in the n-channel MISFET formation region;
(d) after the step (c), forming a first cap film containing zirconium over the second insulating film formed in the n-channel MISFET formation region and over the hard mask film formed in the p-channel MISFET formation region;
(e) after the step (d), performing a heating treatment to the semiconductor substrate to diffuse the zirconium contained in the first cap film into the second insulating film in the n-channel MISFET formation region, and thereby form a first insulating film containing hafnium and zirconium in the re-channel MISFET formation region;
(f) after the step (e), removing the first cap film and the hard mask film which are formed in the p-channel MISFET formation region;
(g) after the step (f), forming a conductor film over the first insulating film formed in the n-channel MISFET formation region and over the second insulating film formed in the p-channel MISFET formation region;
(h) after the step (g), patterning the conductor film to form a first gate electrode in the n-channel MISFET formation region, and form a second gate electrode in the p-channel MISFET formation region;
and
(i) after the step (h), introducing an n-type impurity into the semiconductor substrate in the n-channel MISFET formation region to form a first source region and a first drain region, while introducing a p-type impurity into the semiconductor substrate in the p-channel MISFET formation region to form a second source region and second drain region,
wherein a physical film thickness of the first insulating film is larger than a physical film thickness of the second insulating film, and
wherein a concentration of the zirconium contained in the first insulating film is higher than a concentration of the zirconium contained in the second insulating film.

9 more elements

(a) forming a second insulating film containing hafnium over the semiconductor substrate;
(b) after the step (a), forming a hard mask film over the second insulating film;
(c) after the step (b), patterning the hard mask film to remove the hard mask film formed in the n-channel MISFET formation region;
(d) after the step (c), forming a first cap film containing zirconium over the second insulating film formed in the n-channel MISFET formation region and over the hard mask film formed in the p-channel MISFET formation region;
(e) after the step (d), performing a heating treatment to the semiconductor substrate to diffuse the zirconium contained in the first cap film into the second insulating film in the n-channel MISFET formation region, and thereby form a first insulating film containing hafnium and zirconium in the re-channel MISFET formation region;
(f) after the step (e), removing the first cap film and the hard mask film which are formed in the p-channel MISFET formation region;
(g) after the step (f), forming a first conductor film containing a metal over the first insulating film formed in the n-channel MISFET formation region and over the second insulating film formed in the p-channel MISFET formation region;
(h) after the step (g), patterning the first conductor film to remove the first conductor film formed in the p-channel MISFET formation region;
(i) after the step (h), forming a second conductor film over the first conductor film formed in the n-channel MISFET formation region and over the second insulating film formed in the p-channel MISFET formation region;
(j) after the step (i), patterning the first conductor film and the second conductor film to form a first dummy gate electrode in the n-channel MISFET formation region, and form a second dummy gate electrode in the p-channel MISFET formation region;
(k) after the step (j), introducing an n-type impurity into the semiconductor substrate in the n-channel MISFET formation region to form a first source region and a first drain region, while introducing a p-type impurity into the semiconductor substrate in the p-channel MISFET formation region to form a second source region and a second drain region;
(l) after the step (k), forming, over the semiconductor substrate, an interlayer insulating film covering the first dummy gate electrode and the second dummy gate electrode;
(m) after the step (l), polishing a surface of the interlayer insulating film to expose an upper surface of the first dummy gate electrode and an upper surface of the second dummy gate electrode;
(n) after the step (m), removing the second conductor film forming a part of the first dummy gate electrode to form a first trench in the interlayer insulating film, while removing the second conductor film forming the second dummy gate electrode to form a second trench in the interlayer insulating film;
(o) after the step (n), forming a third conductor film containing a metal over the interlayer insulating film including an inside of the first trench and an inside of the second trench, and forming a fourth conductor film containing a metal over the third conductor film to fill the inside of the first trench and the inside of the second trench with the third conductor film and the fourth conductor film;
and
(p) after the step (o), removing the unneeded third conductor film and the unneeded fourth conductor film which are formed over the interlayer insulating film to form a first gate electrode in the first trench, and form a second gate electrode in the second trench,
wherein a physical film thickness of the first insulating film is larger than a physical film thickness of the second insulating film, and
wherein a concentration of the zirconium contained in the first insulating film is higher than a concentration of the zirconium contained in the second insulating film.

16 more elements

(a) forming a second insulating film containing hafnium over the semiconductor substrate;
(b) after the step (a), forming a first cap film containing zirconium over the second insulating film;
(c) after the step (b), forming a first conductor film containing a metal over the first cap film;
(d) after the step (c), removing the first conductor film and the first cap film which are formed in the p-channel MISFET formation region;
(e) after the step (d), performing a heating treatment to the semiconductor substrate to diffuse the zirconium contained in the first cap film into the second insulating film in the n-channel MISFET formation region, and thereby form a first insulating film containing hafnium and zirconium in the re-channel MISFET formation region;
(f) after the step (e), forming a second conductor film over the first conductor film formed in the n-channel MISFET formation region and over the second insulating film formed in the p-channel MISFET formation region;
(g) after the step (f), patterning the first conductor film and the second conductor film to form a first dummy gate electrode in the n-channel MISFET formation region, and form a second dummy gate electrode in the p-channel MISFET formation region;
(h) after the step (g), introducing an n-type impurity into the semiconductor substrate in the n-channel MISFET formation region to form a first source region and a first drain region, while introducing a p-type impurity into the semiconductor substrate in the p-channel MISFET formation region to form a second source region and a second drain region;
(i) after the step (h), forming, over the semiconductor substrate, an interlayer insulating film covering the first dummy gate electrode and the second dummy gate electrode;
(j) after the step (i), polishing a surface of the interlayer insulating film to expose an upper surface of the first dummy gate electrode and an upper surface of the second dummy gate electrode;
(k) after the step (j), removing the second conductor film forming a part of the first dummy gate electrode to form a first trench in the interlayer insulating film, while removing the second conductor film forming the second dummy gate electrode to form a second trench in the interlayer insulating film;
(l) after the step (k), forming a third conductor film containing a metal over the interlayer insulating film including an inside of the first trench and an inside of the second trench, and forming a fourth conductor film containing a metal over the third conductor film to fill the inside of the first trench and the inside of the second trench with the third conductor film and the fourth conductor film;
and
(m) after the step (l), removing the unneeded third conductor film and the unneeded fourth conductor film which are formed over the interlayer insulating film to form a first gate electrode in the first trench, and form a second gate electrode in the second trench,
wherein a physical film thickness of the first insulating film is larger than a physical film thickness of the second insulating film, and
wherein a concentration of the zirconium contained in the first insulating film is higher than a concentration of the zirconium contained in the second insulating film.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/191,050Filed 26 Jul 2011
Priority: JP 2010-2010498 Sep 2010
Published: 8 Mar 2012
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10B 41/00
Electrically erasable-and-programmable rom [eeprom] devices comprising floating gates
H10D 1/47
Resistors: resistors having no potential barriers
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs