Hybrid channel semiconductor device and method for forming the same

A method for forming a hybrid channel semiconductor device, comprising:

• providing a first semiconductor layer, the first semiconductor layer comprising an NMOS area and a PMOS area, a surface of the first semiconductor layer being covered by a second semiconductor layer, wherein electrons have higher mobility than holes in one of the first semiconductor layer and the second semiconductor layer, and holes have higher mobility than electrons in the other one of the first semiconductor layer and the second semiconductor layer;
• forming a first dummy gate structure on the second semiconductor layer in the NMOS area, forming a second dummy gate structure on the second semiconductor layer in the PMOS area, forming a first source region and a first drain region in the second semiconductor layer and the first semiconductor layer and on respective sides of the first dummy gate structure, forming a second source region and a second drain region in the second semiconductor layer and the first semiconductor layer on respective sides of the second dummy gate structure, the first source region and the first drain region being N-type doped, and the second source region and the second drain region being P-type doped;
• forming an interlayer dielectric layer on the second semiconductor layer and performing planarization on the interlayer dielectric layer, such that the interlayer dielectric layer covers the second semiconductor layer and has a surface aligned with those of the first dummy gate structure and the second dummy gate structure;
• removing the first dummy gate structure to form a first opening, removing the second dummy gate structure to form a second opening;
• and
• forming a first gate structure in the first opening and a second gate structure in the second opening, such that the first opening is filled up with the first gate structure and the second opening is filled up with the second gate structure, wherein the first gate structure is formed on the one of the first semiconductor layer and the second semiconductor layer in which electrons have higher mobility than holes, and the second gate structure is formed on the other one of the first semiconductor layer and the second semiconductor layer in which holes have higher mobility than electrons.