Memory cell, memory device and method for manufacturing memory cell
AssigneeMacronix International Co., Ltd.
InventorsPo-Chou Chen, Yao-Wen Chang, I-Chen Yang
Life of this patent
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Abstract
A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.
Claims21
A memory cell, comprising:
- a substrate, having a first doped region, a second doped region and a channel region located between the first doped region and the second doped region;
- a stacked gate structure, disposed on the channel region, and at least comprising a charge trapping layer and a gate from bottom to top;
- and
- a first isolation structure, disposed in the substrate, connected to the first doped region and extending downwards from the first doped region for a predetermined length, wherein a bottom of the first isolation structure is lower than a bottom of the first doped region.
A memory device, comprising:
- a driving circuit;
- and
- a memory cell array, coupled to the driving circuit, wherein the memory cell array has a plurality of memory cells connected with each other, and each of the memory cells comprises:
- a substrate, having a first doped region, a second doped region and a channel region located between the first doped region and the second doped region;
- a stacked gate structure, disposed on the channel region, and at least comprising a charge trapping layer and a gate from bottom to top;
- and
- a first isolation structure, disposed in the substrate, connected to the first doped region and extending downwards from the first doped region for a predetermined length, wherein a bottom of the first isolation structure is lower than a bottom of the first doped region.
A method for manufacturing a memory cell, comprising:
- providing a substrate, wherein a first doped region, a second doped region and a channel region are already formed in the substrate, and a stacked gate structure is already formed on the channel region, wherein the channel region is located between the first doped region and the second doped region, and the staked gate structure at least comprises a charge trapping layer and a gate from bottom to top;
- and
- forming a first isolation structure in the substrate, the first isolation structure being connected to the first doped region and extending downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure being lower than a bottom of the first doped region.
Dependencies are inferred from the claim text.