Electrical switch using gated resistor structures and three-dimensional integrated circuits using the same
OwnerShu-Lu CHENinventor
Life of this patent
Estimating the term…
Abstract
An electrical switch using a gated resistor structure includes an isolation layer, a doped silicon layer arranged on the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile; a gate layer arranged corresponding to the recessed portion. The recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region. The recessed channel gated resistor structure can be advantageously used to achieve high interconnect density with low thermal budget for 3D integration.
Claims20
An electrical switch using a recessed channel gated resistor structure, including:
- an isolation layer having a first face and a second face opposite to the first face;
- a doped silicon layer arranged on the first face of the isolation layer and having a recessed portion with reduced thickness, the doped silicon layer having a predetermined doping type and a predetermined doping profile;
- a gate dielectric covering at least part of the recessed region of the doped silicon layer;
- a gate layer arranged atop the gate dielectric and covering at least part of the gate dielectric;
- at least one electrical contact connected to the doped silicon layer;
- at least one electrical contact connected to the gate layer;
- wherein the recessed portion in the doped silicon layer has such thickness that a channel defined under the gate can be fully depleted to form a high resistivity region.
An electrical switch using a recessed channel gated resistor structure, including:
- an isolation layer having a first face and a second face opposite to the first face;
- a first silicon layer arranged on the first face of the isolation layer and having a predetermined doping level;
- a second silicon layer arranged on the first silicon layer and having higher doping level than that of the first silicon layer and having the same polarity of doping as the first silicon layer, wherein a recess is defined in the second silicon layer to expose part of the area of the first silicon layer;
- a gate dielectric arranged in the recess and covering at least part of the exposed area of the first silicon layer;
- a gate layer arranged atop the gate dielectric and covering at least part of the gate dielectric;
- at least one electrical contact connected to the second silicon layer;
- at least one electrical contact connected to the gate layer;
- wherein the first silicon layer under the exposed area has such thickness that it can be fully depleted to form a high resistivity region.
A method for three dimensional integration of semiconductor device comprising:
- (a) providing a donor wafer with a first face and a second face opposite to the first face, the donor wafer having at least one buried doped layer located below the first face.
- (b) attaching an acceptor wafer including at least one alignment mark and at least one semiconductor onto the first face the donor wafer;
- (c) removing part of the donor wafer at the direction from the second face and polishing the donor wafer along the direction from the second face until at least one of the peak concentration of the buried doped layer of the donor wafer is exposed;
- (d) with reference to the acceptor wafer, forming a recess structure on the exposed surface of the donor wafer attached to the acceptor wafer;
- (e) forming a gate dielectric to cover at least part of the recess structure;
- (f) forming a gate layer to cover at least part of the gate dielectric;
- (g) with reference to the acceptor wafer, forming at least one contact to the gate layer.
Dependencies are inferred from the claim text.