Non-Volatile Memory System with Modified Memory Cells
AssigneeMoSys, Inc.
InventorJeong Y. Choi
Life of this patent
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Abstract
A method and system in which an embedded memory is fabricated in accordance with a conventional logic process includes one or more non-volatile memory cells, each having an access transistor and a capacitor, which share a common floating gate electrode. The coupling capacitor is provided with a dielectric layer having a thickness greater than the dielectric layer of the access transistor. Regions under the capacitor are implanted with a high dose implant to form an electrically shorted doped area in the channel region of the capacitor. The high dose implant improves the coupling ratio of the capacitor and enhances the uniformity of the capacitor's oxide layer.
Claims29
A method of forming an embedded non-volatile memory system using a conventional logic process comprising:
- fabricating an access transistor gate with a thin dielectric layer;
- and
- fabricating a coupling capacitor with a thick dielectric layer having a thickness greater than the thin dielectric layer.
A method of forming a non-volatile memory cell comprising:
- fabricating an access transistor of the non-volatile memory cell with a thin gate dielectric layer of a logic process;
- and fabricating a coupling capacitor of the non-volatile memory cell with a thick dielectric layer, wherein the thin gate dielectric layer is also used to fabricate transistors external to the non-volatile memory cell.
A nonvolatile memory cell having a single polysilicon layer comprising:
- an access transistor with a thin dielectric layer;
- and a coupling capacitor with a thick dielectric layer having a thickness greater than the dielectric layer of the access transistor.
A non-volatile memory system including memory cells and logic transistors on the same semiconductor substrate, wherein a floating gate is shared by both access transistors and coupling capacitors within the memory cell, the system comprising:
- an access transistor having source/drain regions in the substrate, and a channel between the source and drain regions, said channel being separated from the floating gate by a gate dielectric layer;
- a coupling capacitor having source/drain regions and a channel in the substrate, said channel being separated from the floating gate by a thick dielectric layer, wherein the thick dielectric layer of the coupling capacitor has a thickness greater than the thickness of the gate dielectric layer of the access transistor.
A method of forming a nonvolatile memory cell having an access transistor and a capacitor structure within a semiconductor substrate, the method comprising:
- forming an insulating layer on the semiconductor substrate;
- forming an access transistor gate and a logic gate on the insulating layer;
- forming a capacitor between the gates on the insulating layer;
- providing a first mask on portions of the insulating layer to thereby expose the capacitor area;
- ion implanting an impurity of a first conductivity type at a high dosage level into the capacitor area;
- removing the first mask;
- providing a second mask on the upper surface of the semiconductor substrate to expose only the access transistor gate;
- and
- ion implanting an impurity of a second conductivity type at a low dosage level to form doped regions in the access transistor.
A method of forming an embedded nonvolatile memory system including nonvolatile memory cells and logic transistors on a semiconductor substrate, each of the nonvolatile memory cells having an access transistor and a capacitor area, the method comprising:
- forming shallow trench isolation regions in the semiconductor substrate;
- forming an insulating layer on the semiconductor substrate;
- forming gates for memory and logic devices on the insulating layer;
- disposing a first mask on portions of the insulating layer to expose the capacitor area;
- implanting an impurity of a first conductivity at a high dosage level into the capacitor area;
- removing the first mask;
- providing a second mask on the upper surface of the semiconductor substrate to expose only the access transistor;
- and
- implanting an impurity of a second conductivity type at a low dosage level to form doped regions in the access transistor.
Dependencies are inferred from the claim text.