Integrated electronic device with edge-termination structure and manufacturing method thereof

An integrated circuit, comprising:

• a semiconductor structure, including:
• a first semiconductor layer having a first bandgap;
• a second semiconductor layer disposed over the first layer and having a second bandgap that is narrower than the first bandgap;
• a device region disposed in the second semiconductor layer;
• an edge region disposed in the second semiconductor layer remote from the device region;
• and
• an insulator region disposed over the first semiconductor layer between the device and edge regions.

A system, comprising:

• a first integrated circuit, including:
• a semiconductor structure, including:
• a first semiconductor layer having a first bandgap;
• a second semiconductor layer disposed over the first layer and having a second bandgap that is narrower than the first bandgap;
• a device region disposed in the second semiconductor layer;
• an edge region disposed in the second semiconductor layer remote from the device region;
• and
• an insulator region disposed over the first semiconductor layer between the device and edge regions;
• and
• a second integrated circuit coupled to the first integrated circuit.

A method, comprising:

• generating a voltage across a semiconductor structure having a first semiconductor layer having a first bandgap, a second semiconductor layer disposed over the first layer and having a second bandgap that is narrower than the first bandgap, a device region disposed in the second semiconductor layer, an edge region disposed in the second semiconductor layer remote from the device region, and an insulator region disposed over the first semiconductor layer between the device and edge regions;
• causing a first portion of the voltage to be across the first semiconductor layer;
• and
• causing a second portion of the voltage to be across the device region, the second portion less than the first portion.

An integrated electronic device formed in a body of semiconductor material delimited laterally by a lateral surface, said device comprising:

• a substrate of a first semiconductor material;
• a first epitaxial region of a second semiconductor material, which overlies the substrate and defines a first surface;
• a second epitaxial region of a third semiconductor material, which overlies the first surface and is in direct contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material;
• an active area extending within the second epitaxial region and housing at least one elementary electronic component;
• and
• an edge-termination structure, arranged between the active area and the lateral surface, and comprising a first dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in direct contact with the first epitaxial region.

A method for manufacturing an integrated electronic device, comprising the steps of:

• providing a substrate of a first semiconductor material;
• forming on top of the substrate a first epitaxial region of a second semiconductor material, defining a first surface;
• forming, on top of and in direct contact with the first epitaxial region, a second epitaxial region of a third semiconductor material (Si), the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material;
• forming, within an active area extending within the second epitaxial region, at least one elementary electronic component;
• defining a position of a scribe line with respect to the active area;
• and
• forming, on top of the first surface and in direct contact with the first epitaxial region, and laterally with respect to the second epitaxial region, a first dielectric region, arranged between the active area and the position of the scribe line.