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US 2012/0056146 A1Published application
Resistive memory architectures with multiple memory cells per access device
AssigneeMicron Technology, Inc.
InventorsJun Liu, Mike Violette
Life of this patent
Estimating the term…
Abstract
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.
Claims25
1-61. (canceled)
A resistive memory structure, comprising:
- at least one pair of stacked resistive memory cells;
- a plurality of access devices, each access device being coupled to a respective one of the stacked resistive memory cells via a respective rectifying device;
- and
- a common electrode being positioned between each memory cell in each of the at least one pair of stacked resistive memory cells and coupling each stacked resistive memory cell to a cell select line.
1 more element
A resistive memory structure, comprising:
- at least one pair of stacked resistive memory cells;
- a plurality of access devices, each access device being coupled to a respective one of the stacked resistive memory cells;
- and
- a common electrode being positioned between each memory cell in each of the at least one pair of stacked resistive memory cells and coupling each stacked resistive memory cell to a cell select line via a rectifying device.
1 more element
A phase change memory device, comprising:
- an array of access devices;
- an array of pairs of stacked phase change memory cells, each pair including an upper and a lower phase change memory cell, the lower phase change memory cell being coupled to an access device that is horizontally aligned with the respective stacked pair of memory cells, while the upper phase change memory cell is coupled to an access device that is horizontally offset from the respective stacked pair of memory cells;
- and
- a plurality of rectifying devices, each rectifying device being connected to a memory cell.
1 more element
Dependencies are inferred from the claim text.