Methods for implementing variable speed scan testing
AssigneeEigenix
InventorSung Soo Chung
Life of this patent
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Abstract
In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.
Claims41
A method for performing a scan test for an integrated circuit comprising:
- generating a first set of test vectors configured to operate at a first test clock frequency;
- testing the integrated circuit using the first set of test vectors responsive to the first test clock frequency;
- identifying a first set of outlier cells of the integrated circuit responsive to the testing of the integrated circuit;
- generating a second set of test vectors responsive to the identified outlier cells, wherein the second set of test vectors is configured to operate at a second test clock frequency.
A method for generating test vectors for performing scan tests comprising:
- receiving a first representation of a circuit design;
- choosing a first predetermined test clock frequency from among a set of predetermined frequencies;
- generating a first set of test vectors;
- generating a first set of expected output vectors responsive to the first set of test vectors and further responsive to a first test clock frequency.
A method for designing an integrated circuit comprising:
- developing a first design for an integrated circuit;
- simulating scan tests for the integrated circuit at multiple predetermined test clock frequencies using the first design, wherein the simulation includes a simulation of a test clock generator whose test clock frequency is responsive to m bits of a test vector;
- and
- developing a second design for the integrated circuit responsive to the simulation of the scan test.
A method for designing an integrated circuit comprising:
- developing a first design for an integrated circuit at a first type of synthesis;
- developing a second design for the integrated circuit at a second type of synthesis, wherein the first and second designs correspond to the same functionality of the integrated circuit;
- simulating a scan test for the integrated circuit at a test clock frequency using the second design, wherein the simulation includes a simulation of a test clock generator whose test clock frequency is responsive to m bits of a test vector;
- and
- developing a third design for the integrated circuit at a first type of synthesis responsive to the simulation of the scan test.
A method for designing an integrated circuit comprising:
- developing a first design for an integrated circuit;
- manufacturing the integrated circuit, wherein the first design and the integrated circuit have corresponding functionality;
- testing the integrated circuit using a scan test at a test clock frequency, wherein the a test clock generator generates a signal at the test clock frequency responsive to m bits of a test vector;
- and
- developing a second design for the integrated circuit responsive to results of the scan test.
Dependencies are inferred from the claim text.