Apparatus and system for implementing variable speed scan testing
AssigneeEigenix
InventorSung Soo Chung
Life of this patent
Estimating the term…
Abstract
In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.
Claims41
An apparatus for performing scan testing comprising:
- a clock control register that is m bits long and is configured to receive serial data;
- a clock generator configured to receive as input the m bits of clock control register data and further configured to generate a test clock having a frequency responsive to the m bits of clock control register data;
- and
- an integrated circuit configured with a scan chain for performing scan testing wherein the scan chain is configured to be responsive to the test clock.
An integrated circuit configured to perform scan testing comprising:
- a clock control register that is m bits long and is configured to receive serial data;
- a clock controller configured to receive as input the m bits of clock control register data and further configured to generate a test clock having a frequency responsive to the in bits of clock control register data;
- scan circuitry for performing scan testing wherein the scan circuitry is configured to be responsive to the test clock.
An apparatus for performing, scan testing comprising:
- a field programmable gate array configured to implement:
- a clock control register that is in bits long and is configured to receive serial data;
- a clock controller configured to receive as input the m bits of clock control register data and further configured to generate a test clock having a frequency responsive to the m bits of clock control register data;
- an interface configured to communicate with a scan chain of an integrated circuit, wherein the interface makes available the test clock for use by the scan chain of the integrated circuit.
A method for performing a scan test comprising:
- shifting a test vector that is at least n+m bits long into a clock control register that is m bits long, wherein n bits corresponds to scan test stimulus information and m bits correspond to clock information and wherein m bits of clock information are stored in the clock control register;
- shifting n bits of the test vector into a register of scan chain in an integrated circuit;
- generating a test clock signal at a predetermined frequency responsive to the m bits of clock information;
- generating a launch signal responsive to the test clock signal;
- and
- generating a capture signal responsive to the test clock signal, wherein the capture signal initiates operation to capture a response pattern of the integrated circuit.
Dependencies are inferred from the claim text.