US 2012/0042229 A1 · MULTI-STANDARD VITERBI PROCESSOR

Abstract

Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Claims20

Dependent claims

A Viterbi processor to decode a convolutional code, the processor comprising:

a branch metric unit (BMU) comprising a plurality of branch sub-units that receives a first plurality of input bits from a main memory and outputs a first series of branch metrics, wherein the number of active branch sub-units of the plurality of branch sub-units is based on a programmable generator polynomial and a programmable code rate;
a path metric unit (PMU) comprising a plurality of add-compare-select (ACS) units that receive the first series of branch metrics through a plurality of interconnects and output a first series of path metrics, wherein the configuration of the interconnects is based on a programmable constraint length;
and
a number of active path metric registers in a plurality of path metric registers that receive the first series of path metrics and output a second series of path metrics, wherein the number of active path metrics registers from the plurality of path metric registers is based on the programmable constraint length.

1 more element

Dependencies are inferred from the claim text.

Multi-standard viterbi processor

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Multi-standard viterbi processor

Life of this patent

Abstract

Claims20