Method and apparatus of operating a non-volatile DRAM
AssigneeChip Memory Technology, Inc.
InventorWingyu Lueng
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Abstract
A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate to transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.
Claims15
A non-volatile DRAM memory cell comprising:
- an NMOS pass-gate transistor comprising a drain connected to a bit line a control gate connected to a word line, and a floating gate isolated from and beneath the control gate;
- and
- a capacitor comprising a bottom-plate connected to a source NMOS pass-gate transistor and a top plate is coupled to a common plate node.
Dependencies are inferred from the claim text.