US 2012/0025169 A1 · NANOSTRUCTURE ARRAY TRANSISTOR

Abstract

Transistors and methods for forming transistors from groups of nanostructures are disclosed herein. The transistor may be formed from an array of nanostructures that are grown vertically on a substrate. The nanostructures may have lower, middle and upper segments that may be formed with different materials and/or doping to achieve desired effects. Collectively, the lower segments may form the source or drain, with the middle segments collectively forming the channel. Alternatively, the lower segments could collectively form the emitter or collector, with the middle segments collectively forming the base. Transistor electrodes may be planar metal structures that surround sidewalls of the nanostructures. The transistors may be Field Effect Transistors (FETs) or bipolar junction transistors (BJTs). Heterojunction bipolar junction transistors (HBTs) and high electron mobility transistors (HEMTs) are possible.

Claims37

Dependent claims

A transistor comprising:

an array of nanostructures, wherein nanostructures in the array of nanostructures include first segments, second segments, and third segments, the second segments are between the first and third segments;
a first electrode in electrical contact with the first segments of the nanostructures;
a second electrode surrounding ones of the second segments of the nanostructures;
and
a third electrode in electrical contact with the third segments of the nanostructures.

2 more elements

Dependencies are inferred from the claim text.

Nanostructure array transistor

Life of this patent

Nanostructure array transistor

Life of this patent

Abstract

Claims37