US 2012/0002482 A1 · CHARGE EQUILIBRIUM ACCELERATION IN A FLOATING GATE MEMORY DEVICE VIA A REVERSE FIELD PULSE

Abstract

Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

Claims20

Dependent claims

A method for accelerating charge equilibrium in a memory device, the method comprising:

applying an electric field to a selected memory cell to change an amount of charge stored on a charge storage element in the selected memory cell;
and
reversing the electric field on the selected memory cell without applying a negative voltage with respect to ground to the selected memory cell.

A storage system comprising:

a processor to generate memory control commands;
and
at least one non-volatile memory device coupled to the processor to operate in response to the memory control commands, the at least one memory device comprising:
a memory array comprising two or more memory cells, the memory cells comprising a control gate, a floating gate and a channel;
and
control circuitry coupled to the memory array to control operation of the memory array in response to the memory control commands, the control circuitry being arranged to:
(a) receive a program command from the processor;
(b) apply an electric field to a selected memory cell with a programming pulse at a programming voltage;
(c) reverse the electric field of the selected memory cell by generating a positive voltage in the channel of the selected memory cell and applying a voltage to the control gate of the selected memory cell that is lower than the voltage generated in the channel, but not lower than about 0 volts;
(d) verify the content of the selected memory cell to determine if the selected memory cell is successfully programmed subsequent to reversing the electrical field on the selected memory cell;
and
if the selected memory cell is not yet successfully programmed, the control circuitry to repeat said (b), (c) and (d) until it is determined that the selected memory cell has been successfully programmed;
wherein the programming voltage is incrementally increased prior to one or more repetition.

10 more elements

Dependencies are inferred from the claim text.

Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse

Life of this patent

Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse

Life of this patent

Abstract

Claims20