Fifo buffer system

A FIFO buffer system which temporarily stores received data and outputs the data in an order in which the data was received, the FIFO buffer system comprising:

• a write FIFO buffer to which input data is written;
• a read FIFO buffer from which output data is read;
• a memory interface configured to manage a buffer memory area formed in a save memory, write packet data in the buffer memory area, and read packet data from the buffer memory area;
• a packetizing FIFO buffer configured to receive the input data in common with the write FIFO buffer, packetize the input data into packets having a predetermined packet size, and output the packetized input data as packet data to the memory interface;
• a multiplexer configured to select one of an output of the write FIFO buffer and the packet data output from the memory interface, and output the selected one to the read FIFO buffer;
• and
• a control section configured to control the FIFO buffer system,
• wherein
• the control section controls a selection operation of the multiplexer to switch between a first mode in which the output of the write FIFO buffer is output to the read FIFO buffer and a second mode in which the packet data output from the memory interface is output to the read FIFO buffer, and
• in the first mode, when the read FIFO buffer becomes full, the control section switches the operation mode to the second mode, and in the second mode, when the buffer memory area becomes empty, the control section switches the operation mode to the first mode.