Method for Forming Through-Base Wafer Vias for Fabrication of Stacked Devices
AssigneeDuPont Air Products NanoMaterials LLC
InventorsJames Matthew Henry, Daniel Hernandez Castillo, II
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Abstract
An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV (through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding step prior to CMP processing may not be necessary. The method affords an approximately 1:1 Cu:Si selectivity for removal of silicon and copper under appropriate conditions and the Cu:Si selectivity is tunable by adjustment of levels of some key components.
Claims17
A method for preparing a base silicon wafer for constructing an assembly comprising at least two integrated circuit chips at least one of which is from the base silicon wafer, said method comprising:
- a) providing the base silicon wafer having front and back sides, wherein the front side comprises integrated circuits disposed thereon and wherein the base silicon wafer comprises at least one conductive via comprising conductive metal and extending from the front of the base silicon wafer at least partially through the base silicon wafer;
- b) affixing the front side of the base silicon wafer having integrated circuits thereon to a carrier;
- c) contacting the back side of the base silicon wafer with a polishing pad and a first CMP slurry, said first CMP slurry comprising:
- 1) a liquid carrier;
- 2) hydrogen peroxide at a level of 0.02 weight percent to less than 0.50 weight percent;
- and
- 3) an abrasive;
- and
- d) polishing the backside of the base silicon wafer until at least one conductive via is exposed, wherein silicon on the first base silicon wafer is polished using the first CMP slurry at a removal rate of at least 5,000 angstroms per minute at 6 psi or less of down-force.
A method for preparing a base silicon wafer for constructing an assembly comprising at least two integrated circuit chips at least one of which is from the base silicon wafer, said method comprising:
- a) providing the base silicon wafer having front and back sides, wherein the front side comprises integrated circuits disposed thereon and wherein the base wafer comprises at least one conductive via comprising conductive metal and extending from the front of the base silicon wafer at least partially through the base silicon wafer;
- b) affixing the front side of the base silicon wafer having integrated circuits thereon to a carrier;
- c) contacting the back side of the base silicon wafer with a polishing pad and a first CMP slurry, said first CMP slurry comprising:
- 1) a liquid carrier;
- 2) hydrogen peroxide at a level of 0.02 weight percent to less than 0.50 weight percent;
- and
- 3) an abrasive which may be suspended in the slurry, which may be affixed to a polishing pad, or both;
- and
- d) polishing the backside of the base silicon wafer until at least one conductive via is exposed or further exposed, wherein the base silicon wafer is polished using the first CMP slurry at a rate of at least 5,000 angstroms per minute at 6 psi or less of down-force.
A polishing composition comprising:
- a) an abrasive;
- b) hydrogen peroxide at a level in the range of 0.02 weight percent to less than 0.50 weight percent;
- c) water.
Dependencies are inferred from the claim text.