Charge trapping devices with field distribution layer over tunneling barrier

A method for manufacturing an array of memory cells, the method comprising:

• forming a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers on the surface of a semiconductor substrate, forming a conductive layer on the tunneling barrier dielectric structure, forming a dielectric charge trapping structure on the conductive layer, forming a top dielectric structure on the charge trapping structure, forming a top conductive layer on the top dielectric structure, forming a hard mask layer on the top conductive layer;
• forming a plurality of isolation structures of dielectric material between a plurality of memory cells through all the layers and all the structures and into the substrate;
• stripping of the hard mask layer;
• forming a plurality of rows of memory cells by etching through the tunneling barrier dielectric structure and all the layers and all the structures disposed above the tunneling barrier dielectric structure;
• and
• forming source regions and drain regions by implanting dopants in the surface of the semiconductor substrate, such pairs of the source region and the drain region are separated by a memory cell channel region, and the channel region is below the tunneling barrier dielectric structure.

A method for manufacturing a memory device comprising:

• forming an array of memory cells on a semiconductor substrate arranged in a plurality of NAND strings, the memory cells in the respective NAND strings being coupled in series, and comprising a source region and a drain region in the substrate and separated by a channel region, a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region, a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region, a dielectric charge trapping structure disposed above the conductive layer and above the channel region, a top dielectric structure disposed above the charge trapping structure, and a top conductive layer disposed above the top dielectric structure and above the channel region;
• forming a row decoder, a column decoder, sense amplifiers, at least one input port, at least one output port, data-in structures;
• and
• forming a bias arrangement state machine.