Novel Method to Enhance Channel Stress in CMOS Processes

A method of fabricating an integrated circuit, comprising:

• providing a partially processed silicon substrate with a gate and a channel region formed thereon;
• implanting a source and drain region;
• depositing a sacrificial layer over said silicon substrate;
• planarizing said sacrifical layer;
• prior to annealing said source and drain region, implanting said gate with a species to amorphize a lower portion of said gate without amorphizing an upper portion of the gate using the planarized sacrificial layer to block the amorphizing implant from the source and drain region;
• removing said sacrificial layer;
• applying stress to said channel region;
• and
• with said lower portion of said gate in an amorphous state, perform an anneal of said source and drain regions wherein said anneal converts said lower amorphous portion of said gate to polycrystalline material.