US 2011/0300673 A1 · POST-DISPENSE VACUUM OVEN FOR REDUCING UNDERFILL VOIDS DURING IC ASSEMBLY

Abstract

An IC assembly method for reducing voids in underfill material. An IC die is bonded to a substrate which creates a gap between the IC die and the substrate. An underfill material that has a curing temperature (Tuc) is dispensed around at least one side along a perimeter of the gap, where capillary forces draw the underfill material into the gap to at least partially fill the gap to form an underfilled IC assembly. After the dispensing, a vacuum oven process is applied to the underfilled IC assembly which applies a vacuum of 15 to 140 torr and a temperature that is between Tuc −85° C. and Tuc −5° C., for reducing voids in the underfill material. The underfill material is then cured by heating the underfilled IC assembly to a temperature ≧ Tuc.

Claims18

Dependent claims

An IC assembly method for reducing voids in underfill material, comprising:

bonding an IC die to a substrate, wherein a gap between said IC die and said substrate is created;
dispensing an underfill material having a curing temperature (Tuc) around at least one side along a perimeter of said gap, wherein capillary forces draw said underfill material into said gap to at least partially fill said gap to form an underfilled IC assembly;
after said dispensing, vacuum oven processing said underfilled IC assembly, said vacuum oven processing comprising applying a vacuum of 15 torr to 140 torr and a temperature (Tvo) that is between said Tuc −85° C. and said Tuc −5° C., for reducing said voids in said underfill material, and
curing said underfill material by heating said underfilled IC assembly at a temperature ≧ said Tuc to cure said underfill material.

1 more element

Dependencies are inferred from the claim text.

Post-dispense vacuum oven for reducing underfill voids during ic assembly

Life of this patent

Post-dispense vacuum oven for reducing underfill voids during ic assembly

Life of this patent

Abstract

Claims18