High speed digital to analog converter with reduced spurious outputs

A method comprising:

• scrambling N digital data streams using a scrambling sequence in a first circuit;
• transferring the N scrambled digital data streams and the scrambling sequence over a data bus to a second circuit;
• and
• processing the N scrambled digital data streams in the second circuit using a first processing module to generate M digital data streams, where M and N are integers greater than one;
• further descrambling and processing the output of the first processing module at the second circuit using one or more descrambling and processing modules;
• and
• performing digital to analog conversion on an output of the one or more descrambling and processing modules.

A system comprising:

• a first circuit comprising:
• an analog to digital converter module that receives an analog input and that outputs M digital data streams;
• a scrambling module that receives the M digital data streams and that scrambles the M digital data streams using a scrambling sequence;
• and
• a first processing module that receives the scrambled M digital data streams and that outputs N digital data streams, where N and M are integers greater than one;
• a data bus that receives the N digital data streams;
• and
• a second circuit comprising:
• a second processing module that receives the N digital data streams and that processes the N digital data streams;
• and
• one or more descrambling and processing modules that receive an output of the first processing module, that further process the output of the second processing module, and that descramble the output of the second processing module based on the scrambling sequence.