Noise shaped interpolator and decimator apparatus and method
AssigneeSTMicroelectronics S.r.l.
InventorsSteven R. Norsworthy, Jason Rupert Redgrave
Life of this patent
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Abstract
Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.
Claims21
1-10. (canceled)
Decimator apparatus useful in a communications circuit, comprising:
- a filter:
- a delta-sigma modulator:
- and
- an elastic storage element.
Radio frequency apparatus comprising a fractional-N oscillator having a modulus update frequency.
A method of suppressing phase noise in a radio frequency device having a transmit frequency and receive frequency, the method comprising:
- providing a phase lock loop (PLL) having a modulus;
- and
- updating said modulus at a frequency comprising a multiple or sub-multiple of an offset between said receive frequency and transmit frequency;
- wherein said act of updating reduces the presence of phase noise generated by said PLL at said receive frequency.
A method of operating a fractional-N interpolator apparatus comprising a delta-sigma modulator, first and second clock domains, and an elastic buffer disposed operatively between said clock domains, the method comprising:
- clocking data into said buffer using said first clock domain;
- generating an error signal related to the difference between said first and second clock domains;
- filtering said error signal;
- modulating said filtered error signal;
- and
- generating a clock period signal based at least in part on said modulated filtered signal.
A method of operating a fractional-N interpolation or decimation apparatus comprising a delta-sigma modulator, first and second clock domains, one of said clock domains operating at a speed greater than the other, the method comprising:
- asynchronously clocking data out of or into an elastic storage element disposed between the two clock domains based at least in part on a signal generated by said delta-sigma modulator and counter.
Dependencies are inferred from the claim text.