Communication testing circuit, electronic device, receiving circuit, transmitting circuit, semiconductor integrated circuit, and wafer

A receiving circuit comprising:

• a clock and data recovery circuit that receives a transmission signal generated by modulating serial data converted from a pseudo-random pattern based on a clock signal and recovers the pseudo-random pattern from the transmission signal;
• a detector that compares the recovered pseudo-random pattern with a preset pseudo-random pattern and outputs a signal indicating error information;
• and
• an output terminal of the signal indicating error information.

A transmitting circuit comprising:

• a transmitting unit including
• a spread spectrum clock generator that generates a modulated clock signal by modulating a reference clock signal,
• a pseudo-random binary sequence generator that generates a pseudo-random pattern, and
• a signal generator that generates a transmission signal by modulating the pseudo-random pattern based on the modulated clock signal;
• a control unit that receives a signal indicating error information being a comparison result of the pseudo-random pattern recovered from the transmission signal with a preset pseudo-random pattern, counts a number of errors from the signal indicating error information, and decides a timing margin based on a counting result;
• and
• an input terminal of the signal indicating error information.

A wafer comprising at least a first chip and a second chip adjacent the first chip,

• wherein the first chip has formed thereon a receiving circuit and the second chip has formed thereon a transmitting circuit;
• wherein the receiving circuit is comprised of:
• a clock and data recovery circuit configured to receive a transmission signal and recover a pseudo-random pattern from the transmission signal;
• a detector configured to compare the recovered pseudo-random pattern with a preset pseudo-random pattern and output a signal indicating error information;
• and
• an output terminal for outputting the signal indicating error information;
• and
• wherein the transmitting circuit is comprised of:
• a transmitting unit including a spread spectrum clock generator configured to generate a modulated clock signal by modulating a reference clock signal, a pseudo-random binary sequence generator configured to generate a pseudo-random pattern, and a signal generator configured to generate said transmission signal by modulating the pseudo-random pattern based on the modulated clock signal;
• and
• a control unit configured to receive said signal indicating error information, count a number of errors from the signal indicating error information, and decide a timing margin based on a counting result;
• and
• an input terminal configured to receive said signal indicating error information.