Memory array circuit incorporating multiple array block selection and related method
AssigneeSanDisk 3D LLC
InventorsRoy E. Scheuerlein, Luca G. Fasoli
Life of this patent
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Abstract
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
Claims7
In an integrated circuit having a memory array comprising a plurality of linearly-arranged array blocks, a method comprising:
- simultaneously selecting in a first mode of operation a greater number of array blocks than in a second mode of operation.
An integrated circuit comprising:
- a memory array comprising a plurality of linearly-arranged array blocks, each array block comprising a plurality of memory cells, each memory cell coupled to an associated bit line;
- a first M-bit data bus spanning the plurality of linearly-arranged array blocks;
- a second M-bit data bus spanning the plurality of linearly-arranged array blocks;
- and
- a bit line selection circuit;
- wherein said bit line selection circuit is configured, in a first mode of operation, to couple each of a first plurality M of bit lines within a first selected array block to a respective bus line of the first M-bit data bus, and to couple each of a second plurality M of bit lines within a second selected array block to a respective bus line of the second M-bit data bus;
- and
- wherein said bit line selection circuit is configured, in a second mode of operation, to couple each of a third plurality M of bit lines within a third selected array block to a respective bus line of the first M-bit data bus, and to couple each of a fourth plurality M of bit lines within the third selected array block to a respective bus line of the second M-bit data bus.
Dependencies are inferred from the claim text.