Input/output bank architecture for an integrated circuit

An input/output (I/O) bank disposed within an integrated circuit, the I/O bank comprising:

• a first byte clock group comprising a first clock source configured to clock circuit elements within the first byte clock group operating at approximately a frequency at which a first source synchronous device coupled to the first byte clock group communicates data;
• and
• a second byte clock group comprising a second clock source configured to clock circuit elements within the second byte clock group operating at approximately a frequency at which a second source synchronous device coupled to the second byte clock group communicates data,
• wherein the first clock source is independent of the second clock source.

An integrated circuit comprising:

• an input/output (I/O) bank;
• a plurality of byte clock groups disposed within the I/O bank, wherein each of the plurality of byte clock groups is independently configurable to implement a different source synchronous interface, wherein each byte clock group comprises:
• at least one phaser configured to clock circuit elements of the byte clock group that operate at a frequency at which a source synchronous device communicates data to the byte clock group;
• I/O circuitry comprising a plurality of I/O blocks coupled to a plurality of serializer/deserializers, wherein the I/O circuitry is clocked by the at least one phaser;
• and
• at least one first-in-first-out (FIFO) memory coupled to the I/O circuitry, wherein the at least one FIFO memory comprises a first port clocked at a first frequency and a second port clocked at a second frequency, wherein at least one of the first port or the second port is clocked by the at least one phaser.