Margin Testing of Static Random Access Memory Cells

A method of diagnosing a functional failure in a memory that has failed a functional test, the memory comprising a plurality of memory cells, arranged in rows and columns, the memory cells in each column associated with a pair of complementary bit lines, the memory cells in each row associated with a word line, each memory cell comprised of cross-coupled inverters defining a pair of storage nodes, and a pair of pass transistors for coupling the storage nodes to the bit lines of its column responsive to an active level on its associated word line, the method comprising the steps of:

• biasing the identified memory to a relaxed voltage as compared to the failed functional test;
• evaluating a cell stability margin of a first memory cell in the memory by performing a plurality of operations comprising:
• writing a first data state to the first memory cell and a second data state into at least one memory cell other than the first memory cell in a selected column;
• then precharging the bit lines of the selected column to a precharge voltage;
• then floating the bit lines of the selected column;
• selecting a pulse count;
• during the floating step, driving a number of pulses of an active level to a word line associated with one of the at least one other memory cells, the number of pulses corresponding to the pulse count;
• after the driving step and during the floating step, driving the word line associated with the first memory cell to an active level;
• then precharging the bit lines of the selected column;
• then reading the state of the first memory cell;
• responsive to the reading step reading the first data state from the first memory cell:
• increasing the pulse count;
• and
• then repeating the writing, precharging, floating, driving, precharging, and reading steps;
• responsive to the reading step reading the second data state from the first memory cell:
• decreasing the pulse count;
• and
• then repeating the writing, precharging, floating, driving, precharging, and reading steps;
• and
• identifying the cell stability margin corresponding to a pulse count value causing the first memory cell to change to the second data state;
• evaluating a write margin of the first memory cell in the memory by performing a plurality of operations comprising:
• writing a first data state to the first memory cell and a second data state into at least one memory cell other than the first memory cell in the selected column;
• then precharging the bit lines of the selected column to a precharge voltage;
• then floating the bit lines of the selected column;
• selecting a pulse count;
• during the floating step, driving a number of pulses of an active level to a word line associated with one of the at least one other memory cells, the number of pulses corresponding to the pulse count;
• after the driving step and during the floating step, driving the word line associated with the first memory cell to an active level;
• then precharging the bit lines of the selected column;
• then reading the state of the first memory cell;
• responsive to the reading step reading the first data state from the first memory cell:
• increasing the pulse count;
• and
• then repeating the writing, precharging, floating, driving, precharging, and reading steps;
• responsive to the reading step reading the second data state from the first memory cell:
• decreasing the pulse count;
• and
• then repeating the writing, precharging, floating, driving, precharging, and reading steps;
• and
• identifying the write margin corresponding to a pulse count value causing the first memory cell to change to the second data state;
• and
• evaluating a read margin of the first memory cell in the memory by performing a plurality of operations comprising:
• writing a first data state to the first memory cell and a second data state into a single other memory cell in the selected column;
• then precharging the bit lines of the selected column to a precharge voltage;
• then floating the bit lines of the selected column;
• selecting a pulse count;
• during the floating step, driving a number of pulses of an active level to a word line associated with the first memory cell, the number of pulses corresponding to the pulse count;
• after the driving step and during the floating step, driving the word line associated with the other memory cell to an active level;
• then precharging the bit lines of the selected column;
• then reading the state of the other memory cell;
• responsive to the reading step reading the second data state from the other memory cell:
• increasing the pulse count;
• and
• then repeating the writing, precharging, floating, driving, precharging, and reading steps;
• responsive to the reading step reading the first data state from the other memory cell:
• decreasing the pulse count;
• and
• then repeating the writing, precharging, floating, driving, precharging, and reading steps;
• and
• identifying the read margin corresponding to a pulse count value causing the other memory cell to change to the first data state;
• and
• identifying a worst one of the cell stability margin, write margin, and read margin for the first memory cell of the memory.

A memory in an integrated circuit, comprising:

• a plurality of memory cells, arranged in rows and columns, each memory cell comprised of cross-coupled inverters defining a pair of storage nodes, and a pair of pass transistors, each coupled to one of the storage nodes;
• a plurality of pairs of complementary bit lines, each pair of complementary bit lines associated with a column of memory cells;
• a plurality of word lines, each word line associated with a row of memory cells, and coupled to the pass transistors in each memory cell in its associated row so that an active level on a word line couples the storage nodes of its associated memory cells in the row to the complementary bit lines of the corresponding columns;
• a row decoder, for selectably driving the active level on a selected one of the plurality of word lines in read and write operations;
• precharge circuitry, coupled to each of the complementary bit lines, for precharging the bit lines to a precharge voltage in each memory cycle;
• write circuitry, for writing a data state to a memory cell in a selected column and a selected row;
• sense circuitry, for sensing a data state of a pair of complementary bit lines associated with a selected column;
• and
• test control logic, coupled to the word line driver and to the precharge circuitry, for controlling the precharge circuitry to float the bit lines of a selected column in a test operation, and for controlling the row decoder to drive a selected one of the plurality of word lines to the active level while the precharge circuitry is controlled to float the bit lines of the selected column.