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US 2011/0299348 A1Published application
Semiconductor memory device and integrated circuit
AssigneeHynix Semiconductor Inc.
InventorNak Kyu PARK
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a write control signal generating circuit and a write enable signal generating unit. The write control signal generating circuit is configured to generate a write control signal activated during a time period from an input time point of a read command to an end time point of a data output time period. The write enable signal generating unit is configured to output a write command as a write enable signal in response to the write control signal.
Claims25
A semiconductor memory device comprising:
- a write control signal generating circuit configured to generate a write control signal activated during a time period from an input time point of a read command to an end time point of a data output time period;
- and
- a write enable signal generating unit configured to output a write command as a write enable signal in response to the write control signal.
A semiconductor memory device comprising:
- an On Die Termination (ODT) enable signal generating unit configured to generate an ODT enable signal for controlling an operation of an ODT circuit in response to a snoop read command;
- a control signal generating unit configured to generate a control signal whose activation time period is determined in response to the ODT enable signal;
- a write control signal outputting unit configured to generate a write control signal whose activation time period is determined in response to the control signal and the ODT enable signal;
- and
- a write enable signal generating unit configured to output a write command as a write enable signal according to the write control signal.
2 more elements
An integrated circuit comprising:
- a first semiconductor memory device configured to receive a read command at a first time point and deactivate a first write enable signal during a time period from the first time point to an end time point of a data output time period;
- and
- a second semiconductor memory device configured to receive a snoop read command at the first time point and deactivate a second write enable signal during a time period determined according to a burst length before the data output time period.
Dependencies are inferred from the claim text.