# US 2011/0299345 A1 · Early Read After Write Operation Memory Device, System And Method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2011/0299345 A1 - Document ID: US20110299345A1 - Status: Published application - Kind: A1 - Application number: 12/961,395 - Filed: 2010-12-06 - Published: 2011-12-08 - Earliest claimed: 2002-06-28 - Assignees: Rambus Inc. - Inventors: Richard E. Perego; Frederick A. Ware - Web page: https://patentgrep.com/patent/US20110299345A1 ## CPC - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/106: {Data output latches} - G11C 7/1066: {Output synchronization} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 7/1087: {Data input latches} - G11C 2207/2281: Timing of a read operation - G11C 2207/229: Timing of a write operation - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path. ## Claims ### Claim 1 A memory controller to be coupled to first and second memory banks via a signal path, the memory controller comprising: an interface; and a circuit to output a write address and write data, at the interface, to the first memory bank via the signal path, the circuit to output a read address, at the interface, to the second memory bank via the signal path, wherein the circuit outputs the write data to the first memory bank while outputting the read address to the second memory bank. ### Claim 2 (depends on 1) The memory controller of claim 1, wherein the signal path includes at least a common wire to transfer at least a portion of the write address and at least a portion of the read address to the first and second memory banks. ### Claim 3 (depends on 1) The memory controller of claim 1, wherein the signal path includes a first plurality of wires to transfer control information including the write and read addresses and, wherein the signal path includes a second plurality of wires to transfer data including the write data. ### Claim 4 (depends on 1) The memory controller of claim 1, wherein the circuit outputs at least a portion of the write data to the first memory bank while outputting at least a portion of the read address to the second memory bank. ### Claim 5 (depends on 1) The memory controller of claim 1, wherein the write address is output during a first interval of time and the read address is output during a second interval of time, wherein the second interval of time is immediately after the first interval of time. ### Claim 6 (depends on 5) The memory controller of claim 5, wherein the first interval of time occurs during a first clock cycle of a clock signal and the second interval of time occurs during a second consecutive clock cycle of the clock signal. ### Claim 7 (depends on 1) The memory controller of claim 1, further comprising: a first storage circuit to store a first plurality of commands for the first memory bank; and a second storage circuit to store a second plurality of commands for the second memory bank, wherein the memory controller outputs a first command from the first plurality of commands, the first command associated with the write address, wherein the memory controller outputs a second command from the second plurality of commands, the second command associated with the read address, wherein the first command initiates storing the write data at the write address of the first memory bank and the second command initiates accessing read data at the read address of the second memory bank. ### Claim 8 (depends on 1) The memory controller of claim 1, wherein the first and second memory banks include a first and second array of dynamic random access memory (DRAM) storage cells. ### Claim 9 A memory controller to be coupled to first and second memory banks via a signal path, the memory controller comprising: an interface; a first storage circuit to store a plurality of write commands; and logic to output a write command, at the interface, during a first interval of time to the first memory bank via the signal path, the write command obtained from the plurality of write commands, the logic to output a read command, at the interface, during a second interval of time to the second memory bank via the signal path, wherein the write command initiates storing write data in the first memory bank and the read command initiates accessing read data from the second memory bank, wherein the second interval of time occurs immediately after the first interval of time. ### Claim 10 (depends on 9) The memory controller of claim 9, wherein the signal path includes at least a common wire to transfer at least a portion of the write command and at least a portion of the read command to the first and second memory banks. ### Claim 11 (depends on 9) The memory controller of claim 9, wherein the signal path includes a first plurality of wires to transfer write and read commands and, wherein the signal path includes a second plurality of wires to transfer the read and write data. ### Claim 12 (depends on 9) The memory controller of claim 9, wherein the logic outputs write data associated with the write command and the logic outputs a read address associated with the read command during the second interval of time. ### Claim 13 (depends on 9) The memory controller of claim 9, wherein the write command is output during a first clock cycle of a clock signal and the read command is output during a second consecutive clock cycle of the clock signal. ### Claim 14 (depends on 9) The memory controller of claim 9, wherein the write command is output at a first interface portion of the interface and the write data is output at a second interface portion of the interface, wherein the read data is received at the second interface portion. ### Claim 15 (depends on 9) The memory controller of claim 9, wherein the first and second memory banks include a first and second array of dynamic random access memory (DRAM) storage cells. ### Claim 16 A method of operation in a memory controller having an interface, the memory controller to be coupled to a first memory bank and a second memory bank via common signal path, the method comprising: outputting, at the interface, a write address and write data to the first memory bank via the common signal path; and outputting, at the interface, a read address to the second memory bank via the common signal path, wherein the write address is output during a first interval of time and the read address is output during a second interval of time, wherein the second interval of time is immediately after the first interval of time. ### Claim 17 (depends on 16) The method of claim 16, wherein the common signal path includes at least a common wire to transfer at least a portion of the write address and at least a portion of the read address to the first and second memory banks. ### Claim 18 (depends on 16) The method of claim 16, wherein the common signal path includes a first plurality of wires to transfer write and read addresses and, wherein the common signal path includes a second plurality of wires to transfer data including the write data. ### Claim 19 (depends on 16) The method of claim 16, wherein the first interval of time occurs during a first clock cycle of a clock signal and the second interval of time occurs during a second consecutive clock cycle of the clock signal. ### Claim 20 (depends on 16) The method of claim 16, wherein the memory controller further includes a storage circuit, the method further comprising: outputting a write command with the write address, the write command to initiate a write operation at the write address of the first memory bank; and outputting a read command with the read address, the read command to initiate a read operation at the read address of the second memory bank; obtaining the write command from a plurality of write commands stored in the first storage circuit.