Non-volatile memory device, precharge voltage controlling method thereof, and system including the same
OwnerJin Yub LEEinventor
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device, precharge voltage control method thereof, and system including the same are provided. The non-volatile memory device includes a bit line connected with a non-volatile memory cell, a precharge voltage generation circuit configured to generate a precharge voltage during a precharge operation, and a control circuit configured to apply the precharge voltage of a second level to the bit line in response to a control signal at a first level during a precharge period in a normal read operation and to apply the precharge voltage of a fourth level to the bit line in response to the control signal at the third level during a precharge period in a verify read or erase operation.
Claims20
A non-volatile memory device, comprising:
- a bit line connected with a non-volatile memory cell;
- a precharge voltage generation circuit configured to generate a precharge voltage during a precharge operation;
- and
- a control circuit configured to apply the precharge voltage of a second level to the bit line in response to a control signal at a first level during a precharge period during a normal read operation and to apply the precharge voltage of a fourth level to the bit line in response to the control signal at a third level during a precharge period during a verify read operation or erase operation.
A method of controlling a precharge voltage in a non-volatile memory device, the method comprising:
- applying the precharge voltage of a second level to a bit line in response to a control signal at a first level during a precharge period during a normal read operation;
- and
- applying the precharge voltage of a fourth level to the bit line in response to the control signal at a third level during a precharge period during a verify read or erase operation.
A non-volatile memory device including a plurality of non-volatile memory cells, comprising:
- a bit line connected to at least one the plurality of non-volatile memory cells configured to be controlled during a normal read operation and a verify read or erase operation, each of the normal read operation and the verify read or erase operation including a plurality of periods;
- and
- a control circuit configured to apply a plurality of voltages having different magnitudes to the bit line, wherein at least one of the plurality of voltages applied during one of the plurality of periods of the normal read operation is higher than another of the plurality of voltages applied during a same respective one of the plurality of periods of the verify read or erase operation.
Dependencies are inferred from the claim text.