Methods and apparatus for an isfet
AssigneeFreescale Semiconductor, Inc.
InventorsPatrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Abstract
An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
Claims20
An ISFET structure comprising:
- a substrate;
- a source region and a drain region formed within the substrate and having a channel region provided therebetween;
- a gate dielectric layer formed over the channel region;
- a floating gate structure formed on the gate dielectric over the channel region, the floating gate structure being electrically coupled to a first conductive structure configured to electrically communicate with a fluid having an ion concentration;
- and
- at least one control gate structure electrically coupled to the floating gate structure, the control gate structure configured to accept a voltage bias and to cause the movement of charge between the floating gate structure and the control gate structure in response to the voltage bias.
The ISFET structure of 1, wherein the at least one control gate includes two control gates, each forming a respective capacitor in conjunction with the substrate.
A method of trimming the threshold voltage of an ISFET having a floating gate and a control gate coupled thereto, comprising;
- determining a first threshold voltage value of the ISFET;
- applying a bias voltage to the control gate based on the first threshold voltage such that at least a portion of charge within the ISFET migrates to or from the control gate;
- adjusting the bias voltage until the ISFET has a second threshold voltage substantially equal to a predetermined threshold value;
- and
- removing the bias voltage from the control gate.
A method of forming a CMOS ISFET, comprising:
- providing a substrate;
- forming a floating gate structure over the substrate;
- and
- forming a control gate structure communicatively coupled to the floating gate structure, such that the control gate is configured to receive a bias voltage and effect transfer of charge selectively between the floating gate structure and the control gate structure.
Dependencies are inferred from the claim text.