US 2011/0299330 A1 · PSEUDO PAGE MODE MEMORY ARCHITECTURE AND METHOD

Abstract

A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.

Claims25

Dependent claims

A non-volatile memory array comprising:

a plurality of word-lines;
and
a plurality of columns;
one of said plurality of columns further comprising:
a bistable regenerative circuit having a first terminal coupled to a first signal line, a second terminal coupled to a second signal line, a third terminal coupled to a third signal line, and a fourth terminal coupled to a fourth signal line;
a non-volatile memory cell having a first current carrying terminal coupled to said first signal line, a second current carrying terminal coupled to said second signal line and a control terminal coupled to one of said plurality of word-lines;
a first transistor having a first current carrying terminal coupled to said first terminal of said bistable regenerative circuit, and a second current carrying terminal coupled to a fifth signal line;
and,
a second transistor having a first current carrying terminal coupled to said second terminal of said bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line;
wherein gate terminals of said first and second transistors are coupled to a seventh signal line.

7 more elements

A method of forming a non-volatile memory array, the method comprising:

providing a plurality of word-lines;
providing a plurality of columns;
in one of said plurality of columns:
connecting a first terminal of a bistable regenerative circuit to a first signal line;
connecting a second terminal of said bistable regenerative circuit to a second signal line;
connecting a third terminal of said bistable regenerative circuit to a third signal line;
connecting a fourth terminal of said bistable regenerative circuit to a fourth signal line;
connecting a first current carrying terminal of a non-volatile memory cell to said first signal line;
connecting a second current carrying terminal of said non-volatile memory cell to said second signal line;
connecting a control terminal of said non-volatile memory cell to one of said plurality of word-lines;
connecting a first current carrying terminal of a first transistor to said first terminal of said bistable regenerative circuit;
connecting a second current carrying terminal of said first transistor to a fifth signal line;
connecting a first current carrying terminal of a second transistor to said second terminal of said bistable regenerative circuit;
connecting a second current carrying terminal of said second transistor to a sixth signal line;
and
connecting gate terminals of said first and second transistors to a seventh signal line.

13 more elements

Dependencies are inferred from the claim text.

Pseudo page mode memory architecture and method

Life of this patent

Pseudo page mode memory architecture and method

Life of this patent

Abstract

Claims25