Four-transistor and five-transistor bjt-cmos asymmetric sram cells

A volatile memory cell comprising:

• a retention element implemented as two cross-coupled pairs of bipolar junction transistors (BJTs), wherein in one pair the BJTs are NPN transistors and in another pair the BJTs are PNP transistors, wherein the BJTs in each pair are implemented by overlapping portions of multi layers, such that same layers implement different terminals of the BJTs;
• and
• an access element in operative association with the retention element and further implemented as an at least one CMOS transistor.

A random access memory (RAM) integrated circuit (IC), comprising:

• an array of memory cells, each memory cell comprising a retention element and a CMOS transistor, the retention elements comprising at least one of:
• a NPN and a PNP bipolar junction transistors (BJTs), the retention element operatively engaged to the CMOS transistor, wherein each NPN BJT shares an N layer that sits on a P well of an NMOS transistor and wherein each PNP BJT shares a P layer that sits on an N well of a PMOS transistor.