Tfet based 4t memory devices

A four transistor (4T) memory device, comprising:

• a first pull down transistor and a second pull down transistor in a cross coupled configuration, the first pull down transistor coupling a first multi-stable node and a ground node, and the second pull down transistor coupling a second multi-stable node and the ground node;
• and
• a first access transistor and a second access transistor, the first access transistor coupling a first bit-line to the first multi-stable node, and the second access transistor coupling a second bit-line to the second multi-stable node,
• wherein the first access transistor is configured to conduct current from the first bit-line to the first multi-stable node and to be substantially incapable of conducting current from the first multi-stable node to the first bit-line, and wherein the second access transistor is configured to conduct current from the second bit-line to the second multi-stable node and to be substantially incapable of conducting current from the second multi-stable node to the second bit-line.

A four transistor (4T) memory device, comprising:

• a first diode connected transistor and a second diode connected transistor arranged in series between a supply node and a ground node and defining a common multi-stable node;
• and
• a first access transistor and a second access transistor, each of the first and second access transistors coupling a common bit-line and the common multi-stable node,
• wherein each of the first and second diode connected transistors and each of the first and second access transistors comprises a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction,
• wherein each of the first and second diode connected transistors are arranged in a same current conducting orientation, and wherein each of the first and second access transistors are arranged in opposing current conducting orientations.