US 2011/0299323 A1 · Floating Source Line Architecture for Non-Volatile Memory

Abstract

A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.

Claims20

Dependent claims

A solid-state memory comprising:

a plurality of N non-volatile memory cells where N is greater than two, each memory cell connected to a common floating source line;
and
a write circuit adapted to program a selected memory cell of said plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of said plurality via said common floating source line.

A semiconductor memory device, comprising:

an array of non-volatile memory cells arranged in rows and columns;
a plurality of spaced apart floating source lines each extending along a selected row of memory cells to interconnect the memory cells along each said row;
a plurality of spaced apart bit lines each extending along a selected column of memory cells to interconnect the memory cells along each said column;
and
a write circuit adapted to program a selected memory cell in the array to a selected data state by passing a write current of selected magnitude along the bit line connected to the selected memory cell, through the selected memory cell, and along the floating source line connected to the selected memory cell, wherein a portion of the write current concurrently passes from the floating source line through at least two other memory cells connected thereto and along the respective bit lines connected to said two other memory cells.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/206,550Filed 10 Aug 2011

Priority

17 Nov 2008

Published

8 Dec 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 13/0002
Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00: using resistive RAM [RRAM]…
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 11/16
Using magnetic elements: using elements in which the storage effect is based on magnetic spin effect
G11C 11/1673
Auxiliary circuits: reading or sensing circuits or methods

Floating Source Line Architecture for Non-Volatile Memory

Life of this patent

Floating Source Line Architecture for Non-Volatile Memory

Life of this patent

Abstract

Claims20