Non-volatile semiconductor storage device
AssigneeKabushiki Kaisha Toshiba
InventorFumihiro KONO
Life of this patent
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Abstract
A non-volatile semiconductor storage device includes a memory cell array having plural electrically rewritable memory cells, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner, and a data writing unit having a voltage supply circuit which supplies a voltage needed to write data to the plural memory cells, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data. The data writing unit stops the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plural memory cells, according to the detection result of the resistance state detecting circuit.
Claims20
A non-volatile semiconductor storage device, comprising:
- a memory cell array having a plurality of first wiring lines, a plurality of second wiring lines disposed to intersect the first wiring lines, and a plurality of electrically rewritable memory cells disposed at intersections of the first and second wiring lines, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner;
- and
- a data writing unit that has a voltage supply circuit which supplies a voltage needed to write data to the plurality of memory cells through the first and second wiring lines, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data,
- the data writing unit stopping the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plurality of memory cells, according to the detection result of the resistance state detecting circuit.
A non-volatile semiconductor storage device, comprising:
- a memory cell array having a plurality of first wiring lines, a plurality of second wiring lines disposed to intersect the first wiring lines, and a plurality of electrically rewritable memory cells disposed at intersections of the first and second wiring lines, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner;
- and
- a data writing unit that has a set voltage supply circuit which supplies a voltage needed for a set operation for changing a resistance state of the variable resistive element from a high resistance state to a low resistance state to the plurality of memory cells through the first and second wiring lines, and a set state detecting circuit which detects that the variable resistive element is in the low resistance state based on the voltage applied to the memory cells at the time of the set operation,
- the data writing unit stopping the supply of the set voltage to the memory cell where the resistance state of the variable resistive element becomes the low resistance state, among the plurality of memory cells, according to the detection result of the set state detecting circuit.
A non-volatile semiconductor storage device, comprising:
- a memory cell array having a plurality of first wiring lines, a plurality of second wiring lines disposed to intersect the first wiring lines, and a plurality of electrically rewritable memory cells disposed at intersections of the first and second wiring lines, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner;
- and
- a data writing unit that has a reset voltage supply circuit which supplies a reset voltage needed for a reset operation for changing a resistance state of the variable resistive element from a low resistance state to a high resistance state to the plurality of memory cells through the first and second wiring lines, and a reset state detecting circuit which detects that the variable resistive element is in the high resistance state based on a cell current flowing to the memory cells at the time of the reset operation,
- the data writing unit stopping the supply of the reset voltage to the memory cell where the resistance state of the variable resistive element becomes the high resistance state, among the plurality of memory cells, according to the detection result of the reset state detecting circuit.
Dependencies are inferred from the claim text.