Communication circuit for driving a plurality of devices
AssigneeQUALCOMM Incorporated
InventorQUANG NGUYEN
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AssigneeQUALCOMM Incorporated
InventorQUANG NGUYEN
Estimating the term…
A system and method is provided for transmitting a signal to a plurality of slave devices (e.g., memory devices, etc.) via a communication circuit having a plurality of segments that are substantially equal in length and/or impedance. Specifically, according to one embodiment of the invention, an electronic system includes a processor, a plurality of memory devices, and a communication circuit (i.e., a bus) having a central node and a plurality of segments. Specifically, the plurality of segments are used to connect the plurality of devices (e.g., the processor, the plurality of memory devices) to the central node. For example, the processor is connected to the central node via a primary segment, the first memory device (M0) is connected to the central node via a first segment, etc. In one embodiment of the invention, the plurality of segments are substantially equal in length. In other words, the central node is substantially electrically-equidistant from each memory device. In another embodiment of the invention, the plurality of segments have substantially equal impedances. By arranging the plurality of memory devices in this manner (e.g., substantially electrically-equidistant from the central node, etc.), a well behaved signal can be received at each memory device.
A circuit for transmitting a signal to a plurality of memory devices such that the signal received by a first one of the plurality of memory devices is substantially the same as the signal received by a second one of the plurality of memory devices, comprising:
A method of transmitting a well-behaved signal to a plurality of memory devices, comprising:
The method of claim 14, wherein said step of arranging said plurality of memory traces further comprises arranging a first one of said plurality of memory traces connecting a first one of said plurality of memory interfaces to said central node such that said first one partially overlaps a second one of said plurality of memory traces connecting a second one of said plurality of memory interfaces to said central node.
Dependencies are inferred from the claim text.