Clock multiplying circuit, solid-state imaging device, and phase-shift circuit

A solid-state imaging device comprising:

• plural pixels arranged in a matrix shape in a row direction and a column direction;
• a clock multiplying circuit including
• a first inverter that is ON/OFF-controlled by a positive-phase signal of a first clock signal and includes a current source terminal and a current sync terminal for a control current flowing on an inside when the first inverter is on, a second inverter that is ON/OFF-controlled by a negative-phase signal of the first clock signal and includes a current source terminal and a current sync terminal for a control current flowing on an inside when the second inverter is on, the current source terminal and the current sync terminal of the second inverter being respectively connected to the current source terminal and the current sync terminal of the first inverter,
• a capacitive element provided between an output end of the first inverter and an output end of the second inverter,
• a current supplying unit that increases, if a frequency of the first clock signal increases, the control current and supplies the control current to the current source terminals of the first inverter and the second inverter and outputs, from the current sync terminals of the first inverter and the second inverter, a control current having a current amount same as a current amount of the control current supplied to the current source terminal,
• a differential detecting unit that receives input of a potential difference signal between both electrodes of the capacitive element and generates, on the basis of a comparison result in a median value of a fluctuation range of the potential difference signal, a second clock signal having a phase difference of 90 degrees with respect to the positive-phase signal of the first clock signal, and
• a multiplied-signal generating unit that generates a double signal of the first clock signal on the basis of the first clock signal and the second clock signal;
• a digital-to-analog conversion circuit that is driven by the double signal generated by the clock multiplying circuit and generates a reference voltage signal for analog to digital conversion;
• and
• an analog-to-digital conversion circuit that includes a counter unit driven by the double signal generated by the clock multiplying circuit and converts a pixel value of the pixels into a digital value.

A phase-shift circuit comprising:

• a first inverter that is ON/OFF-controlled by a positive-phase signal of a first clock signal and includes a current source terminal and a current sync terminal for a control current flowing on an inside when the first inverter is on;
• a second inverter that is ON/OFF-controlled by a negative-phase signal of the first clock signal and includes a current source terminal and a current sync terminal for a control current flowing on an inside when the second inverter is on, the current source terminal and the current sync terminal of the second inverter being respectively connected to the current source terminal and the current sync terminal of the first inverter;
• a capacitive element provided between an output end of the first inverter and an output end of the second inverter;
• a current supplying unit that increases, if a frequency of the first clock signal increases, the control current and supplies the control current to the current source terminals of the first inverter and the second inverter and outputs, from the current sync terminals of the first inverter and the second inverter, a control current having a current amount same as a current amount of the control current supplied to the current source terminal;
• and
• a differential detecting unit that receives input of a potential difference signal between both electrodes of the capacitive element and generates, on the basis of a comparison result in a median value of a fluctuation range of the potential difference signal, a second clock signal having a phase difference of 90 degrees with respect to the positive-phase signal of the first clock signal.