Apparatus and method for well buffering
AssigneeSkyworks Solutions, Inc.
InventorsDavid K. Homol, Karl J. Couglar
Life of this patent
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Abstract
Apparatuses and methods for well buffering are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well, and the gate is formed adjacent the well between the source and drain. The source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a gate bias control block for biasing the gate voltage of the switch, a well bias control block for biasing the well voltage of the switch, and a buffer circuit for increasing the impedance between the well bias control block and the well of the switch.
Claims21
An apparatus for biasing one or more switches, the apparatus comprising:
- a first complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well, the source and drain formed in the well, the gate formed adjacent the well between the source and drain, and the source configured to receive a bias voltage from a power amplifier;
- a gate bias control block for biasing the gate voltage of the first switch, the gate bias control block configured to bias the gate voltage of the first switch to at least two voltage levels;
- a well bias control block for biasing the well voltage of the first switch, the well bias control block configured to bias the well voltage of the first switch to at least two voltage levels;
- and
- a buffer circuit for increasing the impedance between the well bias control block and the well of the first switch.
A method of biasing one or more CMOS switches, the method comprising:
- biasing a gate of a first CMOS switch configured to receive a radio frequency signal from a power amplifier, biasing the gate comprising increasing the voltage level of the gate from a first gate voltage level to a second gate voltage level;
- biasing a well of the first CMOS switch, biasing the well comprising increasing the voltage level of the well from a first well voltage level to a second well voltage level;
- and
- buffering the well of the first switch so as to increase the time it takes to increase the voltage level of the well from the first well voltage level to the second well voltage level.
An apparatus for biasing one or more CMOS switches, the apparatus comprising:
- means for biasing a gate of a first CMOS switch configured to receive a radio frequency signal from a power amplifier, the means for biasing the gate configured to bias the gate of the first switch to at least two voltage levels;
- means for biasing a well of the first CMOS switch, the means for biasing the well configured to bias the well of the first switch to at least two voltage levels;
- and
- means for increasing the impedance between the well of the first switch and the means for biasing the well.
Dependencies are inferred from the claim text.