Phase interpolation circuit suitable for wide range frequency input and output characteristics stabilizing method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsBong-Jin KIM, Jongshin SHIN, Hyun-Goo KIM
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Abstract
A phase interpolation circuit includes a waveform shaping unit and a phase interpolator. The waveform shaping unit adaptively waveform-shapes first or second phase offset input clock signal pair that is applied, to output first and second buffered clock signals having a rising time and falling time each of more than about a quarter of a period of the first and second offset input clock signals. The phase interpolator is applied to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal.
Claims20
A phase interpolation circuit, comprising:
- a waveform shaping unit configured to receive a first phase offset input clock signal pair or a second phase offset input clock signal pair, to adaptively waveform-shape the first or second phase offset input clock signal pair, and to output first and second buffered clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of the first and second offset input clock signals;
- and
- a phase interpolator configured to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal.
A method for stabilizing output characteristics of a phase interpolator, the method comprising:
- performing waveform-shaping such that a first phase offset input clock signal pair or a second phase offset input clock signal pair become first and second clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of first and second phase offset input clock signals, in response to a frequency of the first and second phase offset input clock signals applied to the phase interpolator;
- and
- supplying the first and second clock signals to the phase interpolator.
A data processing device, comprising:
- a transmitting module;
- and
- a receiving module having a clock data recovery circuit, the clock data recovery circuit including:
- a phase interpolation circuit including
- a waveform shaping unit configured to receive a first phase offset input clock signal pair or a second phase offset input clock signal pair, to adaptively waveform-shape the first or second phase offset input clock signal pair, and to output first and second buffered clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of the first and second offset input clock signals, and
- a phase interpolator configured to generate a phase interpolation clock signal selected from phases between the first and second buffered clock signals in response to a weight value of a phase interpolation control signal;
- and
- a clock data recovery main part performing a clock data recovery operation using the phase interpolation output clock signal.
An input unit for a phase interpolator, comprising:
- a waveform shaping unit configured to receive a first phase offset input clock signal pair or a second phase offset input clock signal pair, to adaptively waveform-shape the first or second phase offset input clock signal pair, and to output first and second buffered clock signals to the phase interpolator, the first and second buffered clock signals having a rising time and a falling time each of more than about a quarter of T, where T is a period of the first and second offset input clock signals.
Dependencies are inferred from the claim text.