Duty correcting circuit, delay-locked loop circuit and method of correcting duty
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Sik Na, Jun-Bae Kim
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Abstract
The duty correcting circuit includes a duty cycle corrector, a duty detector and a duty correction code generator. The duty cycle corrector corrects a duty cycle of an input clock signal to generate an output clock signal. The duty detector adjusts a delay time of the output clock signal to generate a sampling clock signal, samples the output clock signal in response to the sampling clock signal to generate sample data, and detects a duty of the output clock signal based on logic states of the sample data. Therefore, the duty correcting circuit precisely detects and corrects a duty of the output clock signal.
Claims22
A duty correcting circuit comprising:
- a duty cycle corrector configured to correct a duty cycle of an input clock signal in response to a duty correction code to generate an output clock signal;
- a duty detector configured to,
- adjust a delay time of the output clock signal to generate a sampling clock signal,
- sample the output clock signal in response to the sampling clock signal,
- generate first sample data and second sample data, and
- detect a duty of the output clock signal based on logic states of the first sample data and the second sample data to generate a duty-up signal and a duty-down signal;
- and
- a duty correction code generator configured to generate the duty correction code in response to the duty-up signal and the duty-down signal.
A duty correcting circuit comprising:
- a duty cycle corrector configured to correct a duty cycle of an input clock signal in response to a duty-up signal and a duty-down signal to generate an output clock signal;
- and
- a duty detector configured to,
- delay the output clock signal to generate a delayed output clock signal,
- invert a phase of the delayed output clock signal to generate an inverted and delayed output clock signal,
- synchronize the output clock signal to the inverted and delayed output clock signal,
- sample the output clock signal in response to the inverted and delayed output clock signal to generate first sample data and second sample data, and
- detect a duty of the output clock signal based on logic states of the first sample data and the second sample data to generate the duty-up signal and the duty-down signal.
(canceled)
17-20. (canceled)
A duty correcting circuit comprising:
- a duty cycle corrector configured to generate an output clock signal based on a duty correction code;
- a duty detector configured to,
- detect a duty of the output clock signal based on logic states associated with sampled data,
- generate a duty-up signal and a duty-down signal based on the detected duty;
- and
- a duty correction code generator configured to generate the duty correction code based on the duty-up signal and the duty-down signal.
Dependencies are inferred from the claim text.