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US 2011/0298505 A1Published application
Latency locked loop circuit for driving a buffer circuit
AssigneeSilicon Laboratories Inc.
InventorsJohn M. Khoury, Eduardo Viegas, Richard Beale
Life of this patent
Estimating the term…
Abstract
In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.
Claims28
A circuit comprising:
- a buffer circuit including a buffer input and an output terminal;
- and
- a latency locked loop (LLL) circuit including a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input, the LLL circuit configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.
A device comprising:
- a load circuit;
- a buffer circuit including a buffer input and including a buffer output coupled to the load circuit;
- and
- a latency locked loop (LLL) circuit including an LLL input for receiving a first pulse width modulated (PWM) signal, a feedback input coupled to the buffer output, and an LLL output terminal coupled to the buffer input, the LLL circuit configured to control pulse widths and pulse positions of pulses within an output signal on the output terminal by controlling a propagation delay of individual edge transitions of the first PWM signal.
1 more element
A circuit comprising:
- an H-bridge comprising first and second inputs and first and second outputs;
- and
- a latency locked loop (LLL) circuit including first and second LLL inputs configurable to receive first and second pulse width modulated (PWM) signal, respectively, the LLL circuit further including a first LLL output coupled to the first input of the H-bridge and a second LLL output coupled to the second input of the H-bridge, the LLL circuit configured to automatically control a first variable delay associated with the first LLL input and a second variable delay associated with the second LLL input to provide a substantially constant total propagation delay from the first and second LLL inputs to the first and second outputs of the H-bridge for individual edge transitions within the first and second PWM signals.
A circuit comprising:
- an H-bridge including an input and including an output configurable to provide a pulse width modulated (PWM) output signal to a load circuit;
- and
- a latency locked loop (LLL) circuit including an LLL input for receiving a PWM input signal and including an LLL output coupled to the input of the H-bridge, the LLL circuit configured to measure pulse widths of the PWM output signal and to adjust edge timing of the PWM input signal at the input of the H-bridge to ensure that pulse widths of the PWM output signal are substantially equal to pulse widths of the PWM input signal.
Dependencies are inferred from the claim text.