Dual-Edge Register and the Monitoring Thereof on the Basis of a Clock
AssigneeSTMicroelectronics S.r.l.
InventorSylvain Engels
Life of this patent
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Abstract
Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.
Claims24
A sequential electronic circuit reacting on a rising edge and a falling edge of a clock signal, comprising:
- a first and a second D-type flip-flop;
- a main multiplexer coupled at a first input to the first flip-flop and at a second input to the second flip-flop;
- a first input receiving the clock signal;
- and
- a second input receiving a control signal so as to control the circuit according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10);
- wherein the clock signal used in the normal operating mode is used to gate the circuit during the test operating mode.
A method for checking operation of a sequential electronic circuit reacting on a rising edge and a falling edge of a clock signal, comprising a first and a second D-type flip-flop, a main multiplexer having respective inputs coupled to the respective outputs of the first and second flip-flops, the circuit comprising a first input receiving the clock signal and a second input receiving a control signal so as to control the circuit according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit, characterized in that the clock signal used in the normal operating mode is used to gate the circuit during the test operating mode.
A method of operating a circuit comprising:
- in response to a control signal, selecting one of a data signal and a test signal at the input of a first flip-flop;
- and
- in response to the control signal, selecting one of the data signal and the test signal at the input of a second flip-flop;
- when the control signal is in a first state, passing the data signal from an output of the first flip-flop to a first input of a main multiplexer on a rising edge of a clock signal, and passing the data signal from an output of the second flip-flop to a second input of the main multiplexer on a falling edge of a clock signal;
- and
- when the control signal is in a second state, passing a test signal from the output of the first flip-flop to the first input of the main multiplexer and passing the test signal from the output of the second flip-flop to the second input of the main multiplexer and to the input of the first flip-flop.
A method of operating a sequential electronic circuit comprising:
- receiving a clock signal at a clock input;
- receiving a data signal at a data input;
- receiving a control signal at a control signal input;
- receiving a test signal at a test signal input;
- when the control signal is in a first state, passing the data signal to an output on a rising edge of the clock signal and passing the data signal to the output on a falling edge of the clock signal;
- and
- when the control signal is in a second state, passing the test signal to the output on a falling edge of the clock signal and passing the test signal to a test output on a rising edge of the clock signal.
Dependencies are inferred from the claim text.