Three dimensional interconnect structure and method thereof

A method for forming a three-dimensional interconnect structure, comprising:

• bonding a first substrate comprising at least a device layer and a bulk semiconductor layer to a second substrate having at least one metal pad on its surface;
• etching a via hole through the first substrate and the bonding layer to expose a metal pad on the second substrate;
• depositing a dielectric layer in the via;
• etching an opening in the via dielectric, only over the surface of a metal pad at the bottom of the via;
• plasma treating a region of the metal pad under the opening in the via dielectric;
• and
• depositing a metal in the via and onto the exposed metal pad on the surface of the second substrate.

A method for forming a via interconnect, comprising:

• bonding a first substrate having a contact pad to a second substrate;
• opening a via hole through the second substrate and exposing a surface of the contact pad recessed in the first substrate;
• plasma treating, with a different plasma chemistry than the opening process, the surface of the recessed contact pad to prepare the surface of the contact pad for metallization;
• and
• depositing a via-fill metal onto the treated contact pad.

An electronics package comprising:

• a first substrate having at least one refractory contact pad;
• a second substrate bonded to the first substrate and including electronic devices;
• a via extending through the second substrate to the contact pad of the first substrate
• a via-fill metal disposed in the via and contacting the at least one contact pad;
• and
• a plasma-treated refractory surface interface between the via-fill metal and the contact pad.

An electronics package comprising:

• a first substrate having at least one contact pad;
• a second substrate bonded to the first substrate and including electronic devices;
• a via having an aspect ratio of height to width ranging from 4:1 to 10:1, and extending through the second substrate to the contact pad of the first substrate
• a via-fill metal disposed in the via and contacting the at least one contact pad;
• and
• a plasma-treated surface interface between the via-fill metal and the contact pad.

A system for forming a via interconnect, comprising:

• a bonder configured to bond a first substrate having a contact pad to a second substrate;
• an etcher configured to etch via hole through the second substrate and expose a surface of the contact pad of the first substrate;
• said etcher configured to plasma treat, with a plasma chemistry other than the plasma chemistry for the via hole etch, the surface of the exposed contact pad to prepare the surface of the contact pad for metallization;
• and
• a metallization unit configured to deposit a via-fill metal onto the plasma treated contact pad.