Shallow trench isolation area having buried capacitor
AssigneeInfineon Technologies AG
InventorHartmud Terletzki
Life of this patent
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Abstract
A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.
Claims22
A semiconductor chip, comprising:
- a substrate comprising a surface;
- an active transistor region and a substrate contact region formed on the substrate;
- a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region;
- and
- at least one capacitor at least partially buried in the STI area.
A shallow trench isolation (STI) area disposed between an active transistor region and a substrate contact region of a semiconductor chip, comprising:
- an isolation trench formed into a surface of a substrate of the semiconductor chip, the isolation trench having sidewalls extending into the substrate;
- and
- at least one capacitor which is at least partially buried in the STI area between the sidewalls.
A method to bury at least one capacitor within a semiconductor chip, comprising:
- forming a shallow trench isolation (STI) area in a surface of the semiconductor chip in between an active transistor region and a substrate contact region of the semiconductor chip;
- and
- at least partially burying the at least one capacitor in the STI area.
Dependencies are inferred from the claim text.