Manufacturing method of gate stack and semiconductor device

A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers, comprising:

• forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate;
• conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure;
• and
• selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure.

A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers, comprising:

• removing a replacement gate stack formed in a inter-device isolation dielectric layer to expose the top surface of a semiconductor substrate and sidewalls of spacers within the inter-device isolation dielectric layer;
• conformally depositing a metal layer covering the inter-device isolation dielectric layer and the semiconductor substrate;
• selectively etching the metal layer to remove the portions of the metal layer covering the inter-device isolation dielectric layer and the semiconductor substrate, and only keeping sacrificial oxygen-scavenging metal spacers in the inner periphery of the spacers;
• and
• sequentially forming an interfacial oxide layer, a high-K dielectric layer, and a metal gate electrode on the semiconductor substrate filling the space between the sacrificial oxygen-scavenging metal spacers, so as to form a gate stack structure.

A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers, comprising:

• removing a replacement gate stack formed in a inter-device isolation dielectric layer to expose the top of a semiconductor substrate and sidewalls of spacers in the inter-device isolation dielectric layer;
• conformally depositing a dielectric layer covering the inter-device isolation dielectric layer and the semiconductor substrate;
• conformally depositing a metal layer covering the dielectric layer;
• selectively etching the metal layer and the dielectric layer sequentially to remove the metal layer and the dielectric layer covering the inter-device isolation dielectric layer and the semiconductor substrate, so as to only keep dielectric spacers in the inner periphery of the spacers and sacrificial oxygen-scavenging metal spacers in the inner periphery of the dielectric spacers;
• and
• sequentially forming an interfacial oxide layer, a high-K dielectric layer, and a metal gate electrode filling the space between the sacrificial oxygen-scavenging metal spacers on the semiconductor substrate.

A semiconductor device, comprising:

• a semiconductor substrate;
• a shallow trench isolation structure formed in the semiconductor substrate;
• and
• a gate formed on the semiconductor substrate;
• wherein, the gate comprises:
• a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer, and a metal gate electrode, wherein the interfacial oxide layer is formed on the semiconductor substrate, the high-K dielectric layer is formed on the interfacial oxide layer, and the metal gate electrode is formed on the high-K dielectric layer;
• and
• sacrificial oxygen-scavenging metal spacers formed on the semiconductor substrate surrounding the gate stack structure in the outer periphery of the gate stack structure.

A semiconductor device, comprising:

• a semiconductor substrate;
• a shallow trench isolation structure formed in the semiconductor substrate;
• a inter-device isolation dielectric layer formed on the semiconductor substrate;
• and
• a gate formed on the semiconductor substrate in a region defined by the inter-device isolation dielectric layer,
• wherein the gate comprises:
• spacers formed on the semiconductor substrate in a region defined by the inter-device isolation dielectric layer;
• a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer, and a metal gate electrode, wherein the interfacial oxide layer is formed on the semiconductor substrate in a region between the spacers, the high-K dielectric layer is formed on the interfacial oxide layer, and the metal gate electrode is filled in a region defined by the high-K dielectric layer;
• and
• sacrificial oxygen-scavenging metal spacers formed on the semiconductor substrate in the inner periphery of the spacers and in the outer periphery of the high-K dielectric layer.

A semiconductor device, comprising:

• a semiconductor substrate;
• a shallow trench isolation structure formed in the semiconductor substrate;
• a inter-device isolation dielectric layer formed on the semiconductor substrate;
• and
• a gate formed on the semiconductor substrate in a region defined by the inter-device isolation dielectric layer,
• wherein the gate comprises:
• spacers formed on the semiconductor substrate in the inter-device isolation dielectric layer;
• a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer, and a metal gate electrode, wherein the interfacial oxide layer is formed on the semiconductor substrate in a region between the spacers, the high-K dielectric layer is formed on the interfacial oxide layer, and the metal gate electrode is filled in a region defined by the high-K dielectric layer;
• dielectric spacers formed on the semiconductor substrate in the inner periphery of the spacers and in the outer periphery of the high-K dielectric layer;
• and
• sacrificial oxygen-scavenging metal spacers formed on the dielectric spacers in the inner periphery of the dielectric spacers and in the outer periphery of the high-K dielectric layer.