Vertical Stacking of Field Effect Transistor Structures for Logic Gates

A method comprising:

• creating a vertical structure on a semiconductor substrate, the vertical structure further comprising a first dielectric layer;
• a first conductor layer;
• a second dielectric layer;
• a second conductor layer, a third dielectric layer, a third conductor layer, and a fourth dielectric layer, and a fifth dielectric layer on a vertical side of the vertical structure;
• creating a first field effect transistor (FET) having a source and a drain in the semiconductor substrate;
• creating a second FET orthogonal to the first FET, the second FET using the fifth dielectric layer as a gate dielectric, and using the second conductor layer as a gate electrode;
• creating a third FET parallel to the first FET, the third FET using the fourth dielectric layer as a gate dielectric, and using the third conducting layer as a gate electrode.