US 2011/0298049 A1 · CMOS Device with Raised Source and Drain Regions

Abstract

A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

Claims20

Dependent claims

A semiconductor structure comprising:

a semiconductor substrate comprising a PMOS region and an NMOS region;
a PMOS device in the PMOS region comprising:
a first gate stack on the semiconductor substrate;
a first offset spacer on a sidewall of the first gate stack;
a stressor in the semiconductor substrate and adjacent the first offset spacer;
and
a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor;
and
an NMOS device in the NMOS region comprising:
a second gate stack on the semiconductor substrate;
a second offset spacer on a sidewall of the second gate stack;
a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer;
and
a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate.

11 more elements

A semiconductor structure comprising:

a semiconductor substrate comprising a PMOS region and an NMOS region;
a PMOS device in the PMOS region comprising:
a first gate stack on the semiconductor substrate;
a first offset spacer on a sidewall of the first gate stack;
a stressor in the semiconductor substrate and having a portion under the first offset spacer;
a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has at least a portion higher than a top surface of the semiconductor substrate;
and
a first main spacer on a sidewall of the first offset spacer, wherein the first main spacer has at least a portion on a top surface of the first raised source/drain extension region;
and
an NMOS device in the NMOS region comprising:
a second gate stack on the semiconductor substrate;
a second offset spacer on a sidewall of the second gate stack;
a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer;
a second main spacer on a sidewall of the second offset spacer, wherein the second main spacer has at least a portion on a top surface of the second raised source/drain extension region;
and
a deep source/drain region adjoining the second raised source/drain extension region, wherein a portion of the deep source/drain region lower than a top surface of the semiconductor substrate is free from stressors.

13 more elements

Dependencies are inferred from the claim text.

CMOS Device with Raised Source and Drain Regions

Life of this patent

CMOS Device with Raised Source and Drain Regions

Life of this patent

Abstract

Claims20