Vertical structure nonvolatile memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsBYEONG-IN CHOE, SUNG-IL CHANG, CHANG-SEOK KANG, JIN-SOO LIM
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Abstract
A vertical structure nonvolatile memory device can include a channel layer that extends in a vertical direction on a substrate. A memory cell string includes a plurality of transistors that are disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer. At least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, which includes the channel layer, extends.
Claims20
A vertical structure nonvolatile memory device comprising:
- a channel layer extending in a vertical direction on a substrate;
- and
- a memory cell string comprising a plurality of transistors disposed on the substrate in the vertical direction along a vertical sidewall of the channel layer, wherein at least one of the plurality of transistors includes at least one recess in a gate of the transistor into which at least one protrusion, comprising the channel layer, extends.
The vertical structure nonvolatile memory device of claim 10, wherein the second interlayer insulating layer between the channel layer and the gate electrode has an etch selectivity different from that of the first interlayer insulating layers.
A vertical structure nonvolatile memory device comprising:
- a plurality of transistors in a memory cell string, each including a respective gate electrode;
- a recess in at least one of the gate electrodes defining a portion of a non-planar surface of the at least one gate electrode;
- and
- a channel layer protruding into the recess and conformally on the portion of the non-planar surface.
A system comprising:
- a memory including a vertical structure nonvolatile memory device comprising:
- a plurality of transistors in a memory cell string, each including a respective gate electrode;
- a recess in at least one of the gate electrodes defining a portion of a non-planar surface of the at least one gate electrode;
- and
- a channel layer protruding into the recess and conformally on
- the portion of the non-planar surface, the system further comprising:
- a processor configured to communicate with the memory via a bus;
- and
- an input/output unit configured to communicate with the bus.
Dependencies are inferred from the claim text.